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clk: xilinx: move xlnx_vcu clock driver from soc
The xlnx_vcu driver is actually a clock controller driver which provides clocks that can be used by a driver for the encoder/decoder units. There is no reason to keep this driver in soc. Move the driver to clk. NOTE: The register mapping actually contains registers for AXI performance monitoring, but these are not used by the driver. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -393,6 +393,7 @@ source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/ti/Kconfig"
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source "drivers/clk/ti/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/x86/Kconfig"
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source "drivers/clk/x86/Kconfig"
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source "drivers/clk/xilinx/Kconfig"
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source "drivers/clk/zynqmp/Kconfig"
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source "drivers/clk/zynqmp/Kconfig"
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endif
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endif
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@ -122,6 +122,7 @@ obj-y += versatile/
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ifeq ($(CONFIG_COMMON_CLK), y)
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_X86) += x86/
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obj-$(CONFIG_X86) += x86/
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endif
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endif
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obj-y += xilinx/
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obj-$(CONFIG_ARCH_ZX) += zte/
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obj-$(CONFIG_ARCH_ZX) += zte/
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
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obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
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19
drivers/clk/xilinx/Kconfig
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19
drivers/clk/xilinx/Kconfig
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@ -0,0 +1,19 @@
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# SPDX-License-Identifier: GPL-2.0
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config XILINX_VCU
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tristate "Xilinx VCU logicoreIP Init"
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depends on HAS_IOMEM && COMMON_CLK
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select REGMAP_MMIO
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help
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Provides the driver to enable and disable the isolation between the
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processing system and programmable logic part by using the logicoreIP
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register set. This driver also configures the frequency based on the
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clock information from the logicoreIP register set.
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If you say yes here you get support for the logicoreIP.
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If unsure, say N.
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To compile this driver as a module, choose M here: the
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module will be called xlnx_vcu.
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2
drivers/clk/xilinx/Makefile
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2
drivers/clk/xilinx/Makefile
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
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@ -1,23 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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menu "Xilinx SoC drivers"
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menu "Xilinx SoC drivers"
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config XILINX_VCU
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tristate "Xilinx VCU logicoreIP Init"
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depends on HAS_IOMEM && COMMON_CLK
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select REGMAP_MMIO
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help
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Provides the driver to enable and disable the isolation between the
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processing system and programmable logic part by using the logicoreIP
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register set. This driver also configures the frequency based on the
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clock information from the logicoreIP register set.
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If you say yes here you get support for the logicoreIP.
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If unsure, say N.
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To compile this driver as a module, choose M here: the
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module will be called xlnx_vcu.
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config ZYNQMP_POWER
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config ZYNQMP_POWER
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bool "Enable Xilinx Zynq MPSoC Power Management driver"
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bool "Enable Xilinx Zynq MPSoC Power Management driver"
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depends on PM && ZYNQMP_FIRMWARE
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depends on PM && ZYNQMP_FIRMWARE
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@ -1,4 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
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obj-$(CONFIG_ZYNQMP_POWER) += zynqmp_power.o
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obj-$(CONFIG_ZYNQMP_POWER) += zynqmp_power.o
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obj-$(CONFIG_ZYNQMP_PM_DOMAINS) += zynqmp_pm_domains.o
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obj-$(CONFIG_ZYNQMP_PM_DOMAINS) += zynqmp_pm_domains.o
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