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phy: qcom-qusb2: add QUSB2 support for IPQ5424
Add the phy init sequence for the Super Speed ports found on IPQ5424. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241118052839.382431-3-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -151,6 +151,21 @@ static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
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};
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static const struct qusb2_phy_init_tbl ipq5424_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x00),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc3),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
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};
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static const unsigned int ipq6018_regs_layout[] = {
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[QUSB2PHY_PLL_STATUS] = 0x38,
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[QUSB2PHY_PORT_TUNE1] = 0x80,
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@ -331,6 +346,16 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
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.autoresume_en = BIT(0),
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};
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static const struct qusb2_phy_cfg ipq5424_phy_cfg = {
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.tbl = ipq5424_init_tbl,
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.tbl_num = ARRAY_SIZE(ipq5424_init_tbl),
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.regs = ipq6018_regs_layout,
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.disable_ctrl = POWER_DOWN,
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.mask_core_ready = PLL_LOCKED,
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.autoresume_en = BIT(0),
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};
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static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
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.tbl = qusb2_v2_init_tbl,
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.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
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@ -905,6 +930,9 @@ static const struct phy_ops qusb2_phy_gen_ops = {
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static const struct of_device_id qusb2_phy_of_match_table[] = {
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{
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.compatible = "qcom,ipq5424-qusb2-phy",
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.data = &ipq5424_phy_cfg,
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}, {
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.compatible = "qcom,ipq6018-qusb2-phy",
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.data = &ipq6018_phy_cfg,
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}, {
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