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drm/xe: Add migrate layer functions for SVM support
Add functions which migrate to / from VRAM accepting a single DPA argument (VRAM) and array of dma addresses (SRAM). Used for SVM migrations. v2: - Don't unlock job_mutex in error path of xe_migrate_vram v3: - Kernel doc (Thomas) - Better commit message (Thomas) - s/dword/num_dword (Thomas) - Return error on to large of migration (Thomas) Signed-off-by: Oak Zeng <oak.zeng@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250306012657.3505757-21-matthew.brost@intel.com
This commit is contained in:
Matthew Brost
parent
77613a2e10
commit
9c44fd5f6e
@ -1544,6 +1544,181 @@ void xe_migrate_wait(struct xe_migrate *m)
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dma_fence_wait(m->fence, false);
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}
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static u32 pte_update_cmd_size(u64 size)
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{
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u32 num_dword;
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u64 entries = DIV_ROUND_UP(size, XE_PAGE_SIZE);
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XE_WARN_ON(size > MAX_PREEMPTDISABLE_TRANSFER);
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/*
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* MI_STORE_DATA_IMM command is used to update page table. Each
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* instruction can update maximumly 0x1ff pte entries. To update
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* n (n <= 0x1ff) pte entries, we need:
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* 1 dword for the MI_STORE_DATA_IMM command header (opcode etc)
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* 2 dword for the page table's physical location
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* 2*n dword for value of pte to fill (each pte entry is 2 dwords)
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*/
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num_dword = (1 + 2) * DIV_ROUND_UP(entries, 0x1ff);
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num_dword += entries * 2;
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return num_dword;
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}
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static void build_pt_update_batch_sram(struct xe_migrate *m,
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struct xe_bb *bb, u32 pt_offset,
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dma_addr_t *sram_addr, u32 size)
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{
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u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB];
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u32 ptes;
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int i = 0;
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ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE);
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while (ptes) {
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u32 chunk = min(0x1ffU, ptes);
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bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
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bb->cs[bb->len++] = pt_offset;
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bb->cs[bb->len++] = 0;
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pt_offset += chunk * 8;
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ptes -= chunk;
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while (chunk--) {
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u64 addr = sram_addr[i++] & PAGE_MASK;
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xe_tile_assert(m->tile, addr);
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addr = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe,
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addr, pat_index,
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0, false, 0);
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bb->cs[bb->len++] = lower_32_bits(addr);
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bb->cs[bb->len++] = upper_32_bits(addr);
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}
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}
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}
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enum xe_migrate_copy_dir {
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XE_MIGRATE_COPY_TO_VRAM,
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XE_MIGRATE_COPY_TO_SRAM,
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};
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static struct dma_fence *xe_migrate_vram(struct xe_migrate *m,
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unsigned long npages,
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dma_addr_t *sram_addr, u64 vram_addr,
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const enum xe_migrate_copy_dir dir)
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{
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struct xe_gt *gt = m->tile->primary_gt;
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struct xe_device *xe = gt_to_xe(gt);
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struct dma_fence *fence = NULL;
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u32 batch_size = 2;
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u64 src_L0_ofs, dst_L0_ofs;
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u64 round_update_size;
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struct xe_sched_job *job;
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struct xe_bb *bb;
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u32 update_idx, pt_slot = 0;
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int err;
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if (npages * PAGE_SIZE > MAX_PREEMPTDISABLE_TRANSFER)
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return ERR_PTR(-EINVAL);
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round_update_size = npages * PAGE_SIZE;
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batch_size += pte_update_cmd_size(round_update_size);
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batch_size += EMIT_COPY_DW;
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bb = xe_bb_new(gt, batch_size, true);
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if (IS_ERR(bb)) {
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err = PTR_ERR(bb);
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return ERR_PTR(err);
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}
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build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE,
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sram_addr, round_update_size);
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if (dir == XE_MIGRATE_COPY_TO_VRAM) {
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src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0);
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dst_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, false);
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} else {
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src_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, false);
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dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0);
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}
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bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
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update_idx = bb->len;
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emit_copy(gt, bb, src_L0_ofs, dst_L0_ofs, round_update_size,
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XE_PAGE_SIZE);
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job = xe_bb_create_migration_job(m->q, bb,
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xe_migrate_batch_base(m, true),
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update_idx);
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if (IS_ERR(job)) {
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err = PTR_ERR(job);
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goto err;
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}
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xe_sched_job_add_migrate_flush(job, 0);
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mutex_lock(&m->job_mutex);
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xe_sched_job_arm(job);
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fence = dma_fence_get(&job->drm.s_fence->finished);
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xe_sched_job_push(job);
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dma_fence_put(m->fence);
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m->fence = dma_fence_get(fence);
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mutex_unlock(&m->job_mutex);
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xe_bb_free(bb, fence);
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return fence;
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err:
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xe_bb_free(bb, NULL);
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return ERR_PTR(err);
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}
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/**
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* xe_migrate_to_vram() - Migrate to VRAM
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* @m: The migration context.
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* @npages: Number of pages to migrate.
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* @src_addr: Array of dma addresses (source of migrate)
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* @dst_addr: Device physical address of VRAM (destination of migrate)
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*
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* Copy from an array dma addresses to a VRAM device physical address
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*
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* Return: dma fence for migrate to signal completion on succees, ERR_PTR on
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* failure
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*/
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struct dma_fence *xe_migrate_to_vram(struct xe_migrate *m,
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unsigned long npages,
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dma_addr_t *src_addr,
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u64 dst_addr)
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{
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return xe_migrate_vram(m, npages, src_addr, dst_addr,
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XE_MIGRATE_COPY_TO_VRAM);
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}
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/**
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* xe_migrate_from_vram() - Migrate from VRAM
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* @m: The migration context.
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* @npages: Number of pages to migrate.
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* @src_addr: Device physical address of VRAM (source of migrate)
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* @dst_addr: Array of dma addresses (destination of migrate)
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*
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* Copy from a VRAM device physical address to an array dma addresses
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*
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* Return: dma fence for migrate to signal completion on succees, ERR_PTR on
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* failure
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*/
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struct dma_fence *xe_migrate_from_vram(struct xe_migrate *m,
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unsigned long npages,
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u64 src_addr,
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dma_addr_t *dst_addr)
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{
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return xe_migrate_vram(m, npages, dst_addr, src_addr,
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XE_MIGRATE_COPY_TO_SRAM);
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}
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#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
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#include "tests/xe_migrate.c"
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#endif
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@ -95,6 +95,16 @@ struct xe_migrate_pt_update {
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struct xe_migrate *xe_migrate_init(struct xe_tile *tile);
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struct dma_fence *xe_migrate_to_vram(struct xe_migrate *m,
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unsigned long npages,
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dma_addr_t *src_addr,
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u64 dst_addr);
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struct dma_fence *xe_migrate_from_vram(struct xe_migrate *m,
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unsigned long npages,
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u64 src_addr,
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dma_addr_t *dst_addr);
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struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
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struct xe_bo *src_bo,
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struct xe_bo *dst_bo,
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