Proxmox-Port/linux-loongson
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson synced 2025-09-02 08:32:55 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

arm64: dts: renesas: r8a77990: Create thermal zone to support IPA

Browse Source 
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

In R-Car Gen3, IPA is supported for only one channel
Reason:
  Currently, IPA controls base on only CPU temperature.
  And only one thermal channel is assembled closest
  CPU cores is selected as target of IPA.
  If other channels are used, IPA controlling is not properly.

A single cooling device is described for all A53 CPUs as this
reflects that physically there is only one cooling device present.

This patch improves on an earlier version by:

* Omitting cooling-max-level and cooling-min-level properties which
  are no longer present in mainline as of v4.17
* Removing an unused trip-point0 node sub-property from the trips
  property.
* Defers adding dynamic-power-coefficient properties to a separate patch as
  these are properties of the CPU.

The long signed-off by chain below reflects many revisions, mainly
internal, that this patch has been through.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Dien Pham 2019-05-23 16:25:43 +02:00 committed by Simon Horman
parent eb2cd8c259
commit 8fa7d18f9e
1 changed files with 16 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -84,6 +84,7 @@ a53_0: cpu@0 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0>; reg = <0>;
device_type = "cpu"; device_type = "cpu";
#cooling-cells = <2>;
power-domains = <&sysc R8A77990_PD_CA53_CPU0>; power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>; next-level-cache = <&L2_CA53>;
enable-method = "psci"; enable-method = "psci";
@ -1856,11 +1857,18 @@ prr: chipid@fff00044 {
thermal-zones { thermal-zones {
cpu-thermal { cpu-thermal {
polling-delay-passive = <250>; polling-delay-passive = <250>;
polling-delay = <1000>; polling-delay = <0>;
thermal-sensors = <&thermal>; thermal-sensors = <&thermal 0>;
sustainable-power = <717>;
trips { trips {
cpu-crit { target: trip-point1 {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
sensor1_crit: sensor1-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <2000>;
type = "critical"; type = "critical";
@ -1868,6 +1876,11 @@ cpu-crit {
}; };
cooling-maps { cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&a53_0 0 2>;
contribution = <1024>;
};
}; };
}; };
}; };