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arm64: dts: qcom: add QCS615 platform
Add initial DTSI for QCS615 SoC. Features added in this revision: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - QFPROM - TLMM - Watchdog - RPMH controller - Sleep stats driver - Rpmhpd power controller - Interconnect - GCC and Rpmhcc - QUP with Uart serial support Written with help from Tingguo Cheng (added rpmhpd power controller nodes) Taniya Das (added clocks nodes), and Raviteja Laggyshetty (added interconnect nodes). Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/r/20241104-add_initial_support_for_qcs615-v5-3-9dde8d7b80b0@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Lijuan Gao
Bjorn Andersson
parent
67b8e9473e
commit
8e266654a2
688
arch/arm64/boot/dts/qcom/qcs615.dtsi
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688
arch/arm64/boot/dts/qcom/qcs615.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,qcs615-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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next-level-cache = <&l2_0>;
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#cooling-cells = <2>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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power-domains = <&cpu_pd1>;
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power-domain-names = "psci";
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next-level-cache = <&l2_100>;
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l2_100: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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power-domains = <&cpu_pd2>;
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power-domain-names = "psci";
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next-level-cache = <&l2_200>;
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l2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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power-domains = <&cpu_pd3>;
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power-domain-names = "psci";
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next-level-cache = <&l2_300>;
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l2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x400>;
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enable-method = "psci";
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power-domains = <&cpu_pd4>;
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power-domain-names = "psci";
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next-level-cache = <&l2_400>;
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l2_400: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x500>;
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enable-method = "psci";
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power-domains = <&cpu_pd5>;
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power-domain-names = "psci";
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next-level-cache = <&l2_500>;
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l2_500: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x600>;
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enable-method = "psci";
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power-domains = <&cpu_pd6>;
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power-domain-names = "psci";
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next-level-cache = <&l2_600>;
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#cooling-cells = <2>;
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l2_600: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x700>;
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enable-method = "psci";
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power-domains = <&cpu_pd7>;
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power-domain-names = "psci";
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next-level-cache = <&l2_700>;
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l2_700: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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};
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};
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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idle-states {
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entry-method = "psci";
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little_cpu_sleep_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <549>;
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exit-latency-us = <901>;
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min-residency-us = <1774>;
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local-timer-stop;
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};
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little_cpu_sleep_1: cpu-sleep-0-1 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <702>;
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exit-latency-us = <915>;
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min-residency-us = <4001>;
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local-timer-stop;
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};
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big_cpu_sleep_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <523>;
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exit-latency-us = <1244>;
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min-residency-us = <2207>;
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local-timer-stop;
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};
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big_cpu_sleep_1: cpu-sleep-1-1 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <526>;
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exit-latency-us = <1854>;
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min-residency-us = <5555>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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cluster_sleep_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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};
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cluster_sleep_1: cluster-sleep-1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41001344>;
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entry-latency-us = <3263>;
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exit-latency-us = <4562>;
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min-residency-us = <8467>;
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};
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cluster_sleep_2: cluster-sleep-2 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x4100b344>;
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entry-latency-us = <3638>;
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exit-latency-us = <6562>;
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min-residency-us = <9826>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0 0x80000000 0 0>;
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};
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camnoc_virt: interconnect-0 {
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compatible = "qcom,qcs615-camnoc-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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ipa_virt: interconnect-1 {
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compatible = "qcom,qcs615-ipa-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mc_virt: interconnect-2 {
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compatible = "qcom,qcs615-mc-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_pd0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
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};
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cpu_pd1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
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};
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cpu_pd2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
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};
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cpu_pd3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
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};
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cpu_pd4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
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};
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cpu_pd5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
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};
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cpu_pd6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
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};
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cpu_pd7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
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};
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cluster_pd: power-domain-cluster {
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#power-domain-cells = <0>;
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domain-idle-states = <&cluster_sleep_0
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&cluster_sleep_1
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&cluster_sleep_2>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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smem_region: smem@86000000 {
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compatible = "qcom,smem";
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reg = <0x0 0x86000000 0x0 0x200000>;
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no-map;
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hwlocks = <&tcsr_mutex 3>;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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ranges = <0 0 0 0 0x10 0>;
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#address-cells = <2>;
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#size-cells = <2>;
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gcc: clock-controller@100000 {
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compatible = "qcom,qcs615-gcc";
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reg = <0 0x00100000 0 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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qfprom: efuse@780000 {
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compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
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reg = <0x0 0x00780000 0x0 0x7000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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qupv3_id_0: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x008c0000 0x0 0x6000>;
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ranges;
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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clock-names = "m-ahb",
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"s-ahb";
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#address-cells = <2>;
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#size-cells = <2>;
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status = "disabled";
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uart0: serial@880000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x00880000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
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pinctrl-names = "default";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&aggre1_noc MASTER_QUP_0 0
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&mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0
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&config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core",
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"qup-config";
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power-domains = <&rpmhpd RPMHPD_CX>;
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status = "disabled";
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};
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};
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config_noc: interconnect@1500000 {
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reg = <0x0 0x01500000 0x0 0x5080>;
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compatible = "qcom,qcs615-config-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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system_noc: interconnect@1620000 {
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reg = <0x0 0x01620000 0x0 0x1f300>;
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compatible = "qcom,qcs615-system-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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aggre1_noc: interconnect@1700000 {
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reg = <0x0 0x01700000 0x0 0x3f200>;
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compatible = "qcom,qcs615-aggre1-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mmss_noc: interconnect@1740000 {
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reg = <0x0 0x01740000 0x0 0x1c100>;
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compatible = "qcom,qcs615-mmss-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x20000>;
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#hwlock-cells = <1>;
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};
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||||
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||||
tcsr: syscon@1fc0000 {
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compatible = "qcom,qcs615-tcsr", "syscon";
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reg = <0x0 0x01fc0000 0x0 0x30000>;
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||||
};
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||||
|
||||
tlmm: pinctrl@3100000 {
|
||||
compatible = "qcom,qcs615-tlmm";
|
||||
reg = <0x0 0x03100000 0x0 0x300000>,
|
||||
<0x0 0x03500000 0x0 0x300000>,
|
||||
<0x0 0x03d00000 0x0 0x300000>;
|
||||
reg-names = "east",
|
||||
"west",
|
||||
"south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&tlmm 0 0 123>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
qup_uart0_tx: qup-uart0-tx-state {
|
||||
pins = "gpio16";
|
||||
function = "qup0";
|
||||
};
|
||||
|
||||
qup_uart0_rx: qup-uart0-rx-state {
|
||||
pins = "gpio17";
|
||||
function = "qup0";
|
||||
};
|
||||
};
|
||||
|
||||
dc_noc: interconnect@9160000 {
|
||||
reg = <0x0 0x09160000 0x0 0x3200>;
|
||||
compatible = "qcom,qcs615-dc-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@9680000 {
|
||||
reg = <0x0 0x09680000 0x0 0x3e200>;
|
||||
compatible = "qcom,qcs615-gem-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,qcs615-pdc", "qcom,pdc";
|
||||
reg = <0x0 0x0b220000 0x0 0x30000>,
|
||||
<0x0 0x17c000f0 0x0 0x64>;
|
||||
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
|
||||
interrupt-parent = <&intc>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sram@c3f0000 {
|
||||
compatible = "qcom,rpmh-stats";
|
||||
reg = <0x0 0x0c3f0000 0x0 0x400>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17a00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
||||
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@17c10000 {
|
||||
compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
|
||||
reg = <0x0 0x17c10000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@17c20000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x17c20000 0x0 0x1000>;
|
||||
ranges = <0 0 0 0x20000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
frame@17c21000 {
|
||||
reg = <0x17c21000 0x1000>,
|
||||
<0x17c22000 0x1000>;
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
frame@17c23000 {
|
||||
reg = <0x17c23000 0x1000>;
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c25000 {
|
||||
reg = <0x17c25000 0x1000>;
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c27000 {
|
||||
reg = <0x17c27000 0x1000>;
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c29000 {
|
||||
reg = <0x17c29000 0x1000>;
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2b000 {
|
||||
reg = <0x17c2b000 0x1000>;
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2d000 {
|
||||
reg = <0x17c2d000 0x1000>;
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
apps_rsc: rsc@18200000 {
|
||||
compatible = "qcom,rpmh-rsc";
|
||||
reg = <0x0 0x18200000 0x0 0x10000>,
|
||||
<0x0 0x18210000 0x0 0x10000>,
|
||||
<0x0 0x18220000 0x0 0x10000>;
|
||||
reg-names = "drv-0",
|
||||
"drv-1",
|
||||
"drv-2";
|
||||
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,drv-id = <2>;
|
||||
qcom,tcs-offset = <0xd00>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 2>,
|
||||
<SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>,
|
||||
<CONTROL_TCS 1>;
|
||||
|
||||
label = "apps_rsc";
|
||||
power-domains = <&cluster_pd>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
};
|
||||
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,qcs615-rpmh-clk";
|
||||
clock-names = "xo";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rpmhpd: power-controller {
|
||||
compatible = "qcom,qcs615-rpmhpd";
|
||||
#power-domain-cells = <1>;
|
||||
operating-points-v2 = <&rpmhpd_opp_table>;
|
||||
|
||||
rpmhpd_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
rpmhpd_opp_ret: opp-0 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_min_svs: opp-1 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_low_svs: opp-2 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_svs: opp-3 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_svs_l1: opp-4 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_nom: opp-5 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_nom_l1: opp-6 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_nom_l2: opp-7 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_turbo: opp-8 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_turbo_l1: opp-9 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user