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arm64: dts: qcom: sa8775p: add QCrypto nodes

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Add the QCE and Crypto BAM DMA nodes.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Link: https://lore.kernel.org/r/20241017144500.3968797-3-quic_yrangana@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Yuvaraj Ranganathan 2024-10-17 20:15:00 +05:30 committed by Bjorn Andersson
parent 4d65f3548a
commit 7ff3da43ef
1 changed files with 22 additions and 0 deletions
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22
arch/arm64/boot/dts/qcom/sa8775p.dtsi
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@ -2389,6 +2389,28 @@ ice: crypto@1d88000 {
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
}; };
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
iommus = <&apps_smmu 0x480 0x00>,
<&apps_smmu 0x481 0x00>;
};
crypto: crypto@1dfa000 {
compatible = "qcom,sa8775p-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x480 0x00>,
<&apps_smmu 0x481 0x00>;
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "memory";
};
stm: stm@4002000 { stm: stm@4002000 {
compatible = "arm,coresight-stm", "arm,primecell"; compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x4002000 0x0 0x1000>, reg = <0x0 0x4002000 0x0 0x1000>,