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arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
Add PCIe controllers and PHY nodes. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230118230526.1499328-2-abel.vesa@linaro.org
This commit is contained in:
Abel Vesa
Bjorn Andersson
parent
6c409f633f
commit
7d1158c984
@ -740,9 +740,9 @@ gcc: clock-controller@100000 {
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#reset-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&bi_tcxo_div2>, <&sleep_clk>,
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clocks = <&bi_tcxo_div2>, <&sleep_clk>,
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<0>,
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<&pcie0_phy>,
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<0>,
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<&pcie1_phy>,
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<0>,
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<&pcie_1_phy_aux_clk>,
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<&ufs_mem_phy 0>,
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<&ufs_mem_phy 0>,
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<&ufs_mem_phy 1>,
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<&ufs_mem_phy 1>,
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<&ufs_mem_phy 2>,
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<&ufs_mem_phy 2>,
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@ -1641,6 +1641,213 @@ mmss_noc: interconnect@1780000 {
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qcom,bcm-voters = <&apps_bcm_voter>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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};
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pcie0: pci@1c00000 {
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device_type = "pci";
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compatible = "qcom,pcie-sm8550";
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reg = <0 0x01c00000 0 0x3000>,
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<0 0x60000000 0 0xf1d>,
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<0 0x60000f20 0 0xa8>,
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<0 0x60001000 0 0x1000>,
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<0 0x60100000 0 0x100000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <0>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
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clock-names = "pipe",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"ddrss_sf_tbu",
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"aggre0";
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interconnect-names = "pcie-mem";
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interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;
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iommus = <&apps_smmu 0x1400 0x7f>;
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iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
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<0x100 &apps_smmu 0x1401 0x1>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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power-domains = <&gcc PCIE_0_GDSC>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_default_state>;
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status = "disabled";
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};
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pcie0_phy: phy@1c06000 {
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compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
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reg = <0 0x01c06000 0 0x2000>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&tcsr TCSR_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "rchng",
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"pipe";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "phy";
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assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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power-domains = <&gcc PCIE_0_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "pcie0_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie1: pci@1c08000 {
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device_type = "pci";
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compatible = "qcom,pcie-sm8550";
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reg = <0x0 0x01c08000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf1d>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x1000>,
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<0x0 0x40100000 0x0 0x100000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <1>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
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clock-names = "pipe",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"ddrss_sf_tbu",
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"aggre1",
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"cnoc_pcie_sf_axi";
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assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnect-names = "pcie-mem";
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interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
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iommus = <&apps_smmu 0x1480 0x7f>;
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iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
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<0x100 &apps_smmu 0x1481 0x1>;
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resets = <&gcc GCC_PCIE_1_BCR>,
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<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
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reset-names = "pci",
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"pcie_1_link_down_reset";
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power-domains = <&gcc PCIE_1_GDSC>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
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enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_default_state>;
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status = "disabled";
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};
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pcie1_phy: phy@1c0e000 {
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compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
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reg = <0x0 0x01c0e000 0x0 0x2000>;
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clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&tcsr TCSR_PCIE_1_CLKREF_EN>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "rchng",
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"pipe", "aux_phy";
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resets = <&gcc GCC_PCIE_1_PHY_BCR>,
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<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
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reset-names = "phy", "nocsr";
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assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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power-domains = <&gcc PCIE_1_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "pcie1_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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cryptobam: dma-controller@1dc4000 {
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cryptobam: dma-controller@1dc4000 {
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compatible = "qcom,bam-v1.7.0";
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x01dc4000 0x0 0x28000>;
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reg = <0x0 0x01dc4000 0x0 0x28000>;
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