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arm64: dts: qcom: sc7180: Fix node order

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The SC7180 device tree nodes should be ordered by address. Re-shuffle
some nodes which currently don't follow this convention.

Since we are already moving it add a missing leading zero to the
address in the 'reg' property of the 'interrupt-controller@b220000'
node.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212170824.v2.1.I55198466344789267ed1eb5ec555fd890c9fc6e1@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Matthias Kaehlcke 2019-12-12 17:08:36 -08:00 committed by Bjorn Andersson
parent 8529728f25
commit 7cee5c7428
1 changed files with 37 additions and 37 deletions
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74
arch/arm64/boot/dts/qcom/sc7180.dtsi
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@ -642,16 +642,6 @@ uart11: serial@a94000 {
}; };
}; };
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7180-pdc", "qcom,pdc";
reg = <0 0xb220000 0 0x30000>;
qcom,pdc-ranges = <0 480 15>, <17 497 98>,
<119 634 4>, <124 639 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
tlmm: pinctrl@3500000 { tlmm: pinctrl@3500000 {
compatible = "qcom,sc7180-pinctrl"; compatible = "qcom,sc7180-pinctrl";
reg = <0 0x03500000 0 0x300000>, reg = <0 0x03500000 0 0x300000>,
@ -952,33 +942,6 @@ qspi: spi@88dc000 {
status = "disabled"; status = "disabled";
}; };
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <10>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
usb_1_hsphy: phy@88e3000 { usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sc7180-qusb2-phy"; compatible = "qcom,sc7180-qusb2-phy";
reg = <0 0x088e3000 0 0x400>; reg = <0 0x088e3000 0 0x400>;
@ -1028,6 +991,13 @@ usb_1_ssphy: phy@88e9200 {
}; };
}; };
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
usb_1: usb@a6f8800 { usb_1: usb@a6f8800 {
compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>; reg = <0 0x0a6f8800 0 0x400>;
@ -1072,6 +1042,36 @@ usb_1_dwc3: dwc3@a600000 {
}; };
}; };
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7180-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 15>, <17 497 98>,
<119 634 4>, <124 639 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <10>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
spmi_bus: spmi@c440000 { spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb"; compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>, reg = <0 0x0c440000 0 0x1100>,