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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: qcom: sm8250.dtsi: add display system nodes
Add device tree nodes for mdss, mdp, dsi0/1. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20201203142105.841666-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Dmitry Baryshkov
Bjorn Andersson
parent
221f0ef37f
commit
7c1dffd471
@ -4,10 +4,12 @@
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,sm8250.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-aoss-qmp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 {
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};
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gpu: gpu@3d00000 {
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/*
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* note: the amd,imageon compatible makes it possible
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* to use the drm/msm driver without the display node,
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* make sure to remove it when display node is added
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*/
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compatible = "qcom,adreno-650.2",
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"qcom,adreno",
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"amd,imageon";
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"qcom,adreno";
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#stream-id-cells = <16>;
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reg = <0 0x03d00000 0 0x40000>;
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@ -1809,6 +1805,298 @@ usb_2_dwc3: dwc3@a800000 {
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};
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};
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mdss: mdss@ae00000 {
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compatible = "qcom,sdm845-mdss";
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reg = <0 0x0ae00000 0 0x1000>;
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reg-names = "mdss";
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interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
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<&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
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<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
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interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "nrt_bus", "core";
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assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
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assigned-clock-rates = <460000000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x820 0x402>;
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status = "disabled";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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mdss_mdp: mdp@ae01000 {
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compatible = "qcom,sdm845-dpu";
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reg = <0 0x0ae01000 0 0x8f000>,
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<0 0x0aeb0000 0 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "iface", "bus", "core", "vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <460000000>,
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<19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SM8250_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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mdp_opp_table: mdp-opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-345000000 {
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opp-hz = /bits/ 64 <345000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-460000000 {
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opp-hz = /bits/ 64 <460000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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dsi0: dsi@ae94000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0 0x0ae94000 0 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SM8250_MMCX>;
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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};
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dsi0_phy: dsi-phy@ae94400 {
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compatible = "qcom,dsi-phy-7nm";
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reg = <0 0x0ae94400 0 0x200>,
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<0 0x0ae94600 0 0x280>,
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<0 0x0ae94900 0 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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status = "disabled";
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};
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dsi1: dsi@ae96000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0 0x0ae96000 0 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SM8250_MMCX>;
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phys = <&dsi1_phy>;
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phy-names = "dsi";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi1_out: endpoint {
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};
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};
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};
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};
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dsi1_phy: dsi-phy@ae96400 {
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compatible = "qcom,dsi-phy-7nm";
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reg = <0 0x0ae96400 0 0x200>,
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<0 0x0ae96600 0 0x280>,
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<0 0x0ae96900 0 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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status = "disabled";
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dsi_opp_table: dsi-opp-table {
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compatible = "operating-points-v2";
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sm8250-dispcc";
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reg = <0 0x0af00000 0 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<&sleep_clk>;
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clock-names = "bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_link_clk_divsel_ten",
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"dp_vco_divided_clk_src_mux",
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"dptx1_phy_pll_link_clk",
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"dptx1_phy_pll_vco_div_clk",
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"dptx2_phy_pll_link_clk",
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"dptx2_phy_pll_vco_div_clk",
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"edp_phy_pll_link_clk",
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"edp_phy_pll_vco_div_clk",
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"sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8250-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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