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dt-bindings: pinctrl: qcom: Add SM4450 pinctrl
Add device tree binding Documentation details for Qualcomm SM4450 TLMM device. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20231212094900.12615-2-quic_tengfan@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Tengfei Fan
Linus Walleij
parent
caf08a8250
commit
7bf8b78f86
151
Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml
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151
Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM4450 TLMM block
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maintainers:
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- Tengfei Fan <quic_tengfan@quicinc.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sm4450-pinctrl
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 68
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gpio-line-names:
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maxItems: 136
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm4450-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm4450-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm4450-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"
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- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
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atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
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atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng,
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
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dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c,
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jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
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mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws,
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mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
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mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk,
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phase_flag0, phase_flag1, phase_flag10, phase_flag11,
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phase_flag12, phase_flag13, phase_flag14, phase_flag15,
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phase_flag16, phase_flag17, phase_flag18, phase_flag19,
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phase_flag2, phase_flag20, phase_flag21, phase_flag22,
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phase_flag23, phase_flag24, phase_flag25, phase_flag26,
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phase_flag27, phase_flag28, phase_flag29, phase_flag3,
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phase_flag30, phase_flag31, phase_flag4, phase_flag5,
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phase_flag6, phase_flag7, phase_flag8, phase_flag9,
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pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2,
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prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
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qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
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qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
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qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
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qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
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qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
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qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
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qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
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qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0,
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tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
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tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk,
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uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
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uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1,
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vsense_trigger ]
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required:
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- pins
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sm4450-tlmm";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 137>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio23";
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function = "qup1_se2";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio22";
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function = "qup1_se2";
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bias-disable;
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};
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};
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};
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...
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