mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-05 11:53:41 +00:00
dt-bindings: fsl-imx-sdma: Convert imx sdma to DT schema
Convert the i.MX SDMA binding to DT schema format using json-schema. The compatibles fsl,imx31-to1-sdma, fsl,imx31-to2-sdma, fsl,imx35-to1-sdma and fsl,imx35-to2-sdma are not used. So need to delete it. The compatibles fsl,imx50-sdma, fsl,imx6sll-sdma and fsl,imx6sl-sdma are added. The original binding don't list all compatible used. In addition, add new peripheral types HDMI Audio. Signed-off-by: Joy Zou <joy.zou@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221115093823.2879128-2-joy.zou@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Joy Zou
Vinod Koul
parent
dcca9d045c
commit
7bdbd87d40
149
Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml
Normal file
149
Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml
Normal file
@ -0,0 +1,149 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Joy Zou <joy.zou@nxp.com>
|
||||||
|
|
||||||
|
allOf:
|
||||||
|
- $ref: dma-controller.yaml#
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
oneOf:
|
||||||
|
- items:
|
||||||
|
- enum:
|
||||||
|
- fsl,imx50-sdma
|
||||||
|
- fsl,imx51-sdma
|
||||||
|
- fsl,imx53-sdma
|
||||||
|
- fsl,imx6q-sdma
|
||||||
|
- fsl,imx7d-sdma
|
||||||
|
- const: fsl,imx35-sdma
|
||||||
|
- items:
|
||||||
|
- enum:
|
||||||
|
- fsl,imx6sx-sdma
|
||||||
|
- fsl,imx6sl-sdma
|
||||||
|
- const: fsl,imx6q-sdma
|
||||||
|
- items:
|
||||||
|
- const: fsl,imx6ul-sdma
|
||||||
|
- const: fsl,imx6q-sdma
|
||||||
|
- const: fsl,imx35-sdma
|
||||||
|
- items:
|
||||||
|
- const: fsl,imx6sll-sdma
|
||||||
|
- const: fsl,imx6ul-sdma
|
||||||
|
- items:
|
||||||
|
- const: fsl,imx8mq-sdma
|
||||||
|
- const: fsl,imx7d-sdma
|
||||||
|
- items:
|
||||||
|
- enum:
|
||||||
|
- fsl,imx8mp-sdma
|
||||||
|
- fsl,imx8mn-sdma
|
||||||
|
- fsl,imx8mm-sdma
|
||||||
|
- const: fsl,imx8mq-sdma
|
||||||
|
- items:
|
||||||
|
- enum:
|
||||||
|
- fsl,imx25-sdma
|
||||||
|
- fsl,imx31-sdma
|
||||||
|
- fsl,imx35-sdma
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
interrupts:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
fsl,sdma-ram-script-name:
|
||||||
|
$ref: /schemas/types.yaml#/definitions/string
|
||||||
|
description: Should contain the full path of SDMA RAM scripts firmware.
|
||||||
|
|
||||||
|
"#dma-cells":
|
||||||
|
const: 3
|
||||||
|
description: |
|
||||||
|
The first cell: request/event ID
|
||||||
|
|
||||||
|
The second cell: peripheral types ID
|
||||||
|
enum:
|
||||||
|
- MCU domain SSI: 0
|
||||||
|
- Shared SSI: 1
|
||||||
|
- MMC: 2
|
||||||
|
- SDHC: 3
|
||||||
|
- MCU domain UART: 4
|
||||||
|
- Shared UART: 5
|
||||||
|
- FIRI: 6
|
||||||
|
- MCU domain CSPI: 7
|
||||||
|
- Shared CSPI: 8
|
||||||
|
- SIM: 9
|
||||||
|
- ATA: 10
|
||||||
|
- CCM: 11
|
||||||
|
- External peripheral: 12
|
||||||
|
- Memory Stick Host Controller: 13
|
||||||
|
- Shared Memory Stick Host Controller: 14
|
||||||
|
- DSP: 15
|
||||||
|
- Memory: 16
|
||||||
|
- FIFO type Memory: 17
|
||||||
|
- SPDIF: 18
|
||||||
|
- IPU Memory: 19
|
||||||
|
- ASRC: 20
|
||||||
|
- ESAI: 21
|
||||||
|
- SSI Dual FIFO: 22
|
||||||
|
description: needs firmware more than ver 2
|
||||||
|
- Shared ASRC: 23
|
||||||
|
- SAI: 24
|
||||||
|
- HDMI Audio: 25
|
||||||
|
|
||||||
|
The third cell: transfer priority ID
|
||||||
|
enum:
|
||||||
|
- High: 0
|
||||||
|
- Medium: 1
|
||||||
|
- Low: 2
|
||||||
|
|
||||||
|
gpr:
|
||||||
|
$ref: /schemas/types.yaml#/definitions/phandle
|
||||||
|
description: The phandle to the General Purpose Register (GPR) node
|
||||||
|
|
||||||
|
fsl,sdma-event-remap:
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||||
|
maxItems: 2
|
||||||
|
items:
|
||||||
|
items:
|
||||||
|
- description: GPR register offset
|
||||||
|
- description: GPR register shift
|
||||||
|
- description: GPR register value
|
||||||
|
description: |
|
||||||
|
Register bits of sdma event remap, the format is <reg shift val>.
|
||||||
|
The order is <RX>, <TX>.
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
maxItems: 2
|
||||||
|
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: ipg
|
||||||
|
- const: ahb
|
||||||
|
|
||||||
|
iram:
|
||||||
|
$ref: /schemas/types.yaml#/definitions/phandle
|
||||||
|
description: The phandle to the On-chip RAM (OCRAM) node.
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- interrupts
|
||||||
|
- fsl,sdma-ram-script-name
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
sdma: dma-controller@83fb0000 {
|
||||||
|
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
||||||
|
reg = <0x83fb0000 0x4000>;
|
||||||
|
interrupts = <6>;
|
||||||
|
#dma-cells = <3>;
|
||||||
|
fsl,sdma-ram-script-name = "sdma-imx51.bin";
|
||||||
|
};
|
||||||
|
|
||||||
|
...
|
||||||
@ -1,118 +0,0 @@
|
|||||||
* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible : Should be one of
|
|
||||||
"fsl,imx25-sdma"
|
|
||||||
"fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
|
|
||||||
"fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
|
|
||||||
"fsl,imx51-sdma"
|
|
||||||
"fsl,imx53-sdma"
|
|
||||||
"fsl,imx6q-sdma"
|
|
||||||
"fsl,imx7d-sdma"
|
|
||||||
"fsl,imx6ul-sdma"
|
|
||||||
"fsl,imx8mq-sdma"
|
|
||||||
"fsl,imx8mm-sdma"
|
|
||||||
"fsl,imx8mn-sdma"
|
|
||||||
"fsl,imx8mp-sdma"
|
|
||||||
The -to variants should be preferred since they allow to determine the
|
|
||||||
correct ROM script addresses needed for the driver to work without additional
|
|
||||||
firmware.
|
|
||||||
- reg : Should contain SDMA registers location and length
|
|
||||||
- interrupts : Should contain SDMA interrupt
|
|
||||||
- #dma-cells : Must be <3>.
|
|
||||||
The first cell specifies the DMA request/event ID. See details below
|
|
||||||
about the second and third cell.
|
|
||||||
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
|
|
||||||
scripts firmware
|
|
||||||
|
|
||||||
The second cell of dma phandle specifies the peripheral type of DMA transfer.
|
|
||||||
The full ID of peripheral types can be found below.
|
|
||||||
|
|
||||||
ID transfer type
|
|
||||||
---------------------
|
|
||||||
0 MCU domain SSI
|
|
||||||
1 Shared SSI
|
|
||||||
2 MMC
|
|
||||||
3 SDHC
|
|
||||||
4 MCU domain UART
|
|
||||||
5 Shared UART
|
|
||||||
6 FIRI
|
|
||||||
7 MCU domain CSPI
|
|
||||||
8 Shared CSPI
|
|
||||||
9 SIM
|
|
||||||
10 ATA
|
|
||||||
11 CCM
|
|
||||||
12 External peripheral
|
|
||||||
13 Memory Stick Host Controller
|
|
||||||
14 Shared Memory Stick Host Controller
|
|
||||||
15 DSP
|
|
||||||
16 Memory
|
|
||||||
17 FIFO type Memory
|
|
||||||
18 SPDIF
|
|
||||||
19 IPU Memory
|
|
||||||
20 ASRC
|
|
||||||
21 ESAI
|
|
||||||
22 SSI Dual FIFO (needs firmware ver >= 2)
|
|
||||||
23 Shared ASRC
|
|
||||||
24 SAI
|
|
||||||
|
|
||||||
The third cell specifies the transfer priority as below.
|
|
||||||
|
|
||||||
ID transfer priority
|
|
||||||
-------------------------
|
|
||||||
0 High
|
|
||||||
1 Medium
|
|
||||||
2 Low
|
|
||||||
|
|
||||||
Optional properties:
|
|
||||||
|
|
||||||
- gpr : The phandle to the General Purpose Register (GPR) node.
|
|
||||||
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
|
|
||||||
<reg shift val>.
|
|
||||||
reg is the GPR register offset.
|
|
||||||
shift is the bit position inside the GPR register.
|
|
||||||
val is the value of the bit (0 or 1).
|
|
||||||
|
|
||||||
Examples:
|
|
||||||
|
|
||||||
sdma@83fb0000 {
|
|
||||||
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
|
||||||
reg = <0x83fb0000 0x4000>;
|
|
||||||
interrupts = <6>;
|
|
||||||
#dma-cells = <3>;
|
|
||||||
fsl,sdma-ram-script-name = "sdma-imx51.bin";
|
|
||||||
};
|
|
||||||
|
|
||||||
DMA clients connected to the i.MX SDMA controller must use the format
|
|
||||||
described in the dma.txt file.
|
|
||||||
|
|
||||||
Examples:
|
|
||||||
|
|
||||||
ssi2: ssi@70014000 {
|
|
||||||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
|
||||||
reg = <0x70014000 0x4000>;
|
|
||||||
interrupts = <30>;
|
|
||||||
clocks = <&clks 49>;
|
|
||||||
dmas = <&sdma 24 1 0>,
|
|
||||||
<&sdma 25 1 0>;
|
|
||||||
dma-names = "rx", "tx";
|
|
||||||
fsl,fifo-depth = <15>;
|
|
||||||
};
|
|
||||||
|
|
||||||
Using the fsl,sdma-event-remap property:
|
|
||||||
|
|
||||||
If we want to use SDMA on the SAI1 port on a MX6SX:
|
|
||||||
|
|
||||||
&sdma {
|
|
||||||
gpr = <&gpr>;
|
|
||||||
/* SDMA events remap for SAI1_RX and SAI1_TX */
|
|
||||||
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
The fsl,sdma-event-remap property in this case has two values:
|
|
||||||
- <0 15 1> means that the offset is 0, so GPR0 is the register of the
|
|
||||||
SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
|
|
||||||
Setting bit 15 to 1 selects SAI1_RX.
|
|
||||||
- <0 16 1> means that the offset is 0, so GPR0 is the register of the
|
|
||||||
SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
|
|
||||||
Setting bit 16 to 1 selects SAI1_TX.
|
|
||||||
Loading…
Reference in New Issue
Block a user