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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: qcom: Adds base SM4450 DTSI
Add based DTSI for SM4450 SoC and includes base description of CPUs and interrupt-controller which helps to boot to shell with dcc console on boards with this SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20230731080043.38552-4-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Tengfei Fan
Bjorn Andersson
parent
2b1fd18fe5
commit
7a1fd03e74
431
arch/arm64/boot/dts/qcom/sm4450.dtsi
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431
arch/arm64/boot/dts/qcom/sm4450.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks{
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <800>;
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exit-latency-us = <750>;
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min-residency-us = <4090>;
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local-timer-stop;
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};
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <600>;
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exit-latency-us = <1550>;
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min-residency-us = <4791>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <1050>;
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exit-latency-us = <2500>;
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min-residency-us = <5309>;
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};
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CLUSTER_SLEEP_1: cluster-sleep-1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41003344>;
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entry-latency-us = <1561>;
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exit-latency-us = <2801>;
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min-residency-us = <8550>;
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};
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};
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};
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memory@a0000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0xa0000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CLUSTER_PD: power-domain-cpu-cluster0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
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};
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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#hwlock-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm4450-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
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qcom,pdc-ranges = <0 480 94>, <94 494 31>,
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<125 63 1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
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<0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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};
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timer@17420000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x17420000 0x0 0x1000>;
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ranges = <0 0 0 0x20000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@17421000 {
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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frame@17423000 {
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reg = <0x17423000 0x1000>;
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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frame@17425000 {
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reg = <0x17425000 0x1000>;
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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frame@17427000 {
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reg = <0x17427000 0x1000>;
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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frame@17429000 {
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reg = <0x17429000 0x1000>;
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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frame@1742b000 {
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reg = <0x1742b000 0x1000>;
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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frame@1742d000 {
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reg = <0x1742d000 0x1000>;
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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