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drm/xe/mtl: Map PPGTT as CPU:WC

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On MTL and beyond, the GPU performs non-coherent accesses to the PPGTT
page tables.  These page tables should be mapped as CPU:WC.

Removes CAT errors triggered by xe_exec_basic@once-basic on MTL:

   xe 0000:00:02.0: [drm:__xe_pt_bind_vma [xe]] Preparing bind, with range [1a0000...1a0fff) engine 0000000000000000.
   xe 0000:00:02.0: [drm:xe_vm_dbg_print_entries [xe]] 1 entries to update
   xe 0000:00:02.0: [drm:xe_vm_dbg_print_entries [xe]]  0: Update level 3 at (0 + 1) [0...8000000000) f:0
   xe 0000:00:02.0: [drm] Engine memory cat error: guc_id=2
   xe 0000:00:02.0: [drm] Engine memory cat error: guc_id=2
   xe 0000:00:02.0: [drm] Timedout job: seqno=4294967169, guc_id=2, flags=0x4

v2:
 - Rename to XE_BO_PAGETABLE to make it more clear that this BO is the
   pagetable itself, rather than just being bound in the PPGTT.  (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230725003433.1992137-3-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-07-24 17:34:34 -07:00 committed by Rodrigo Vivi
parent 9700a1df0a
commit 7a060d786c
3 changed files with 15 additions and 5 deletions
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16
drivers/gpu/drm/xe/xe_bo.c
View File

@ -301,6 +301,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
struct xe_device *xe = xe_bo_device(bo); struct xe_device *xe = xe_bo_device(bo);
struct xe_ttm_tt *tt; struct xe_ttm_tt *tt;
unsigned long extra_pages; unsigned long extra_pages;
enum ttm_caching caching = ttm_cached;
int err; int err;
tt = kzalloc(sizeof(*tt), GFP_KERNEL); tt = kzalloc(sizeof(*tt), GFP_KERNEL);
@ -314,10 +315,17 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size), extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size),
PAGE_SIZE); PAGE_SIZE);
/* TODO: Select caching mode */ /*
err = ttm_tt_init(&tt->ttm, &bo->ttm, page_flags, * Display scanout is always non-coherent with the CPU cache.
bo->flags & XE_BO_SCANOUT_BIT ? ttm_write_combined : ttm_cached, *
extra_pages); * For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and
* require a CPU:WC mapping.
*/
if (bo->flags & XE_BO_SCANOUT_BIT ||
(xe->info.graphics_verx100 >= 1270 && bo->flags & XE_BO_PAGETABLE))
caching = ttm_write_combined;
err = ttm_tt_init(&tt->ttm, &bo->ttm, page_flags, caching, extra_pages);
if (err) { if (err) {
kfree(tt); kfree(tt);
return NULL; return NULL;

1
drivers/gpu/drm/xe/xe_bo.h
View File

@ -40,6 +40,7 @@
#define XE_BO_DEFER_BACKING BIT(9) #define XE_BO_DEFER_BACKING BIT(9)
#define XE_BO_SCANOUT_BIT BIT(10) #define XE_BO_SCANOUT_BIT BIT(10)
#define XE_BO_FIXED_PLACEMENT_BIT BIT(11) #define XE_BO_FIXED_PLACEMENT_BIT BIT(11)
#define XE_BO_PAGETABLE BIT(12)
/* this one is trigger internally only */ /* this one is trigger internally only */
#define XE_BO_INTERNAL_TEST BIT(30) #define XE_BO_INTERNAL_TEST BIT(30)
#define XE_BO_INTERNAL_64K BIT(31) #define XE_BO_INTERNAL_64K BIT(31)

3
drivers/gpu/drm/xe/xe_pt.c
View File

@ -221,7 +221,8 @@ struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,
XE_BO_CREATE_VRAM_IF_DGFX(tile) | XE_BO_CREATE_VRAM_IF_DGFX(tile) |
XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT | XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT |
XE_BO_CREATE_PINNED_BIT | XE_BO_CREATE_PINNED_BIT |
XE_BO_CREATE_NO_RESV_EVICT); XE_BO_CREATE_NO_RESV_EVICT |
XE_BO_PAGETABLE);
if (IS_ERR(bo)) { if (IS_ERR(bo)) {
err = PTR_ERR(bo); err = PTR_ERR(bo);
goto err_kfree; goto err_kfree;