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iio: adc: adi-axi-adc: add support for AD7606 register writing

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Since we must access the bus parallel bus using a custom procedure,
let's add a specialized compatible, and define specialized callbacks for
writing the registers using the parallel interface.

Signed-off-by: Guillaume Stols <gstols@baylibre.com>
Co-developed-by: Angelo Dureghello <adureghello@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Link: https://patch.msgid.link/20250210-wip-bl-ad7606_add_backend_sw_mode-v4-6-160df18b1da7@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Guillaume Stols 2025-02-10 17:10:56 +01:00 committed by Jonathan Cameron
parent a4ab57debd
commit 79c47485e4
1 changed files with 81 additions and 0 deletions
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81
drivers/iio/adc/adi-axi-adc.c
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@ -27,6 +27,7 @@
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include "ad7606_bus_iface.h"
/*
* Register definitions:
* https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
@ -73,6 +74,12 @@
#define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4)
#define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0)
#define ADI_AXI_REG_CONFIG_WR 0x0080
#define ADI_AXI_REG_CONFIG_RD 0x0084
#define ADI_AXI_REG_CONFIG_CTRL 0x008c
#define ADI_AXI_REG_CONFIG_CTRL_READ 0x03
#define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01
#define ADI_AXI_ADC_MAX_IO_NUM_LANES 15
#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
@ -80,6 +87,10 @@
ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
ADI_AXI_REG_CHAN_CTRL_ENABLE)
#define ADI_AXI_REG_READ_BIT 0x8000
#define ADI_AXI_REG_ADDRESS_MASK 0xff00
#define ADI_AXI_REG_VALUE_MASK 0x00ff
struct axi_adc_info {
unsigned int version;
const struct iio_backend_info *backend_info;
@ -311,6 +322,75 @@ static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name);
}
static int axi_adc_raw_write(struct iio_backend *back, u32 val)
{
struct adi_axi_adc_state *st = iio_backend_get_priv(back);
regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, val);
regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL,
ADI_AXI_REG_CONFIG_CTRL_WRITE);
fsleep(100);
regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00);
fsleep(100);
return 0;
}
static int axi_adc_raw_read(struct iio_backend *back, u32 *val)
{
struct adi_axi_adc_state *st = iio_backend_get_priv(back);
regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL,
ADI_AXI_REG_CONFIG_CTRL_READ);
fsleep(100);
regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, val);
regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00);
fsleep(100);
return 0;
}
static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val)
{
struct adi_axi_adc_state *st = iio_backend_get_priv(back);
int addr;
guard(mutex)(&st->lock);
/*
* The address is written on the highest weight byte, and the MSB set
* at 1 indicates a read operation.
*/
addr = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT;
axi_adc_raw_write(back, addr);
axi_adc_raw_read(back, val);
/* Write 0x0 on the bus to get back to ADC mode */
axi_adc_raw_write(back, 0);
return 0;
}
static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val)
{
struct adi_axi_adc_state *st = iio_backend_get_priv(back);
u32 buf;
guard(mutex)(&st->lock);
/* Write any register to switch to register mode */
axi_adc_raw_write(back, 0xaf00);
buf = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) |
FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val);
axi_adc_raw_write(back, buf);
/* Write 0x0 on the bus to get back to ADC mode */
axi_adc_raw_write(back, 0);
return 0;
}
static void axi_adc_free_buffer(struct iio_backend *back,
struct iio_buffer *buffer)
{
@ -498,6 +578,7 @@ static const struct axi_adc_info adc_ad7606 = {
/* Match table for of_platform binding */
static const struct of_device_id adi_axi_adc_of_match[] = {
{ .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic },
{ .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 },
{ /* end of list */ }
};
MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);