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drm/xe/dp: Enable DP tunneling

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Enable the DP tunneling functionality in the xe driver.

v2: Keep using IS_ENABLED() for kconfig options. (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250114122857.1050090-1-imre.deak@intel.com
This commit is contained in:
Imre Deak 2025-01-14 14:28:57 +02:00
parent fd95e73deb
commit 73900dce57
3 changed files with 20 additions and 2 deletions
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5
drivers/gpu/drm/i915/display/intel_dp_tunnel.h
View File

@ -20,7 +20,8 @@ struct intel_dp;
struct intel_encoder; struct intel_encoder;
struct intel_link_bw_limits; struct intel_link_bw_limits;
#if IS_ENABLED(CONFIG_DRM_I915_DP_TUNNEL) && defined(I915) #if (IS_ENABLED(CONFIG_DRM_I915_DP_TUNNEL) && defined(I915)) || \
(IS_ENABLED(CONFIG_DRM_XE_DP_TUNNEL) && !defined(I915))
int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx); int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx);
void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp); void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp);
@ -127,6 +128,6 @@ intel_dp_tunnel_mgr_init(struct intel_display *display)
static inline void intel_dp_tunnel_mgr_cleanup(struct intel_display *display) {} static inline void intel_dp_tunnel_mgr_cleanup(struct intel_display *display) {}
#endif /* CONFIG_DRM_I915_DP_TUNNEL */ #endif /* CONFIG_DRM_I915_DP_TUNNEL || CONFIG_DRM_XE_DP_TUNNEL */
#endif /* __INTEL_DP_TUNNEL_H__ */ #endif /* __INTEL_DP_TUNNEL_H__ */

14
drivers/gpu/drm/xe/Kconfig
View File

@ -59,6 +59,20 @@ config DRM_XE_DISPLAY
help help
Disable this option only if you want to compile out display support. Disable this option only if you want to compile out display support.
config DRM_XE_DP_TUNNEL
bool "Enable DP tunnel support"
depends on DRM_XE
depends on USB4
select DRM_DISPLAY_DP_TUNNEL
default y
help
Choose this option to detect DP tunnels and enable the Bandwidth
Allocation mode for such tunnels. This allows using the maximum
resolution allowed by the link BW on all displays sharing the
link BW, for instance on a Thunderbolt link.
If in doubt say "Y".
config DRM_XE_FORCE_PROBE config DRM_XE_FORCE_PROBE
string "Force probe xe for selected Intel hardware IDs" string "Force probe xe for selected Intel hardware IDs"
depends on DRM_XE depends on DRM_XE

3
drivers/gpu/drm/xe/Makefile
View File

@ -301,6 +301,9 @@ ifeq ($(CONFIG_DEBUG_FS),y)
i915-display/intel_pipe_crc.o i915-display/intel_pipe_crc.o
endif endif
xe-$(CONFIG_DRM_XE_DP_TUNNEL) += \
i915-display/intel_dp_tunnel.o
obj-$(CONFIG_DRM_XE) += xe.o obj-$(CONFIG_DRM_XE) += xe.o
obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/ obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/