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arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level

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OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.

As the attached OSPI device is only known about at the board integration
level, these nodes should only be enabled when provided with this
information.

Disable the OSPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-6-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Andrew Davis 2023-08-09 19:38:06 -05:00 committed by Nishanth Menon
parent 46d0c519e4
commit 73676c480b
4 changed files with 4 additions and 15 deletions
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10
arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
View File

@ -580,16 +580,6 @@ &main_sdhci1 {
disable-wp;
};
&ospi0 {
/* Unused */
status = "disabled";
};
&ospi1 {
/* Unused */
status = "disabled";
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";

2
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
View File

@ -378,6 +378,7 @@ ospi0: spi@47040000 {
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ospi1: spi@47050000 {
@ -392,6 +393,7 @@ ospi1: spi@47050000 {
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};

6
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View File

@ -594,6 +594,7 @@ &main_sdhci1 {
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
@ -657,11 +658,6 @@ partition@3fc0000 {
};
};
&ospi1 {
/* Unused */
status = "disabled";
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";

1
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
View File

@ -202,6 +202,7 @@ eeprom@50 {
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;