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spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -3,7 +3,11 @@
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nandcore-objs := core.o bbt.o
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obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
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obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
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ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
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obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
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else
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obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
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endif
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obj-y += onenand/
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obj-y += raw/
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obj-y += spi/
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@ -936,6 +936,15 @@ config SPI_QCOM_QSPI
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help
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QSPI(Quad SPI) driver for Qualcomm QSPI controller.
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config SPI_QPIC_SNAND
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bool "QPIC SNAND controller"
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depends on ARCH_QCOM || COMPILE_TEST
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select MTD
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help
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QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
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QPIC controller supports both parallel nand and serial nand.
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This config will enable serial nand driver for QPIC controller.
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config SPI_QUP
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tristate "Qualcomm SPI controller with QUP interface"
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depends on ARCH_QCOM || COMPILE_TEST
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@ -117,6 +117,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o
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obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
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obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
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obj-$(CONFIG_SPI_QUP) += spi-qup.o
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obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
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obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
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1631
drivers/spi/spi-qpic-snand.c
Normal file
1631
drivers/spi/spi-qpic-snand.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -325,6 +325,10 @@ struct nandc_regs {
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__le32 read_location_last1;
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__le32 read_location_last2;
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__le32 read_location_last3;
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__le32 spi_cfg;
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__le32 num_addr_cycle;
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__le32 busy_wait_cnt;
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__le32 flash_feature;
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__le32 erased_cw_detect_cfg_clr;
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__le32 erased_cw_detect_cfg_set;
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@ -339,6 +343,7 @@ struct nandc_regs {
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*
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* @core_clk: controller clock
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* @aon_clk: another controller clock
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* @iomacro_clk: io macro clock
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*
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* @regs: a contiguous chunk of memory for DMA register
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* writes. contains the register values to be
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@ -348,6 +353,7 @@ struct nandc_regs {
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* initialized via DT match data
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*
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* @controller: base controller structure
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* @qspi: qpic spi structure
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* @host_list: list containing all the chips attached to the
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* controller
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*
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@ -392,6 +398,7 @@ struct qcom_nand_controller {
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const struct qcom_nandc_props *props;
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struct nand_controller *controller;
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struct qpic_spi_nand *qspi;
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struct list_head host_list;
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union {
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