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drm/amdgpu: Fix xgmi v6.4.1 link status reporting

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Use the right register offsets for getting link status.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2025-03-27 09:34:15 +05:30 committed by Alex Deucher
parent d53a64e9ee
commit 6dee64e765
1 changed files with 18 additions and 6 deletions
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24
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
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@ -296,15 +296,27 @@ static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = {
static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link_num) static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link_num)
{ {
const u32 smnpcs_xgmi3x16_pcs_state_hist1 = 0x11a00070; const u32 smn_xgmi_6_4_pcs_state_hist1[2] = { 0x11a00070, 0x11b00070 };
const int xgmi_inst = 2; const u32 smn_xgmi_6_4_1_pcs_state_hist1[2] = { 0x11b00070,
u32 link_inst; 0x12100070 };
u32 i, n;
u64 addr; u64 addr;
link_inst = global_link_num % xgmi_inst; switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {
case IP_VERSION(6, 4, 0):
n = ARRAY_SIZE(smn_xgmi_6_4_pcs_state_hist1);
addr = smn_xgmi_6_4_pcs_state_hist1[global_link_num % n];
break;
case IP_VERSION(6, 4, 1):
n = ARRAY_SIZE(smn_xgmi_6_4_1_pcs_state_hist1);
addr = smn_xgmi_6_4_1_pcs_state_hist1[global_link_num % n];
break;
default:
return U32_MAX;
}
addr = (smnpcs_xgmi3x16_pcs_state_hist1 | (link_inst << 20)) + i = global_link_num / n;
adev->asic_funcs->encode_ext_smn_addressing(global_link_num / xgmi_inst); addr += adev->asic_funcs->encode_ext_smn_addressing(i);
return RREG32_PCIE_EXT(addr); return RREG32_PCIE_EXT(addr);
} }