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drm/msm/dpu: Add support for MSM8917
Add support for MSM8917, which has MDP5 v1.15. It looks like trimmed down version of MSM8937. Even fewer PP, LM and no DSI1. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [Remove intr_start from CTLs config, reword the commit] Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/617311/ Link: https://lore.kernel.org/r/20240930-dpu-msm8953-msm8996-v2-4-594c3e3190b4@mainlining.org
This commit is contained in:
Dmitry Baryshkov
parent
c079680bb0
commit
62af6e1cb5
187
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
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187
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
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@ -0,0 +1,187 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DPU_1_14_MSM8917_H
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#define _DPU_1_14_MSM8917_H
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static const struct dpu_caps msm8917_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
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.max_mixer_blendstages = 0x4,
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.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
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.pixel_ram_size = 16 * 1024,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_mdp_cfg msm8917_mdp[] = {
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{
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.name = "top_0",
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.base = 0x0, .len = 0x454,
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.features = BIT(DPU_MDP_VSYNC_SEL),
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.clk_ctrls = {
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[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
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[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
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[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
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},
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},
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};
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static const struct dpu_ctl_cfg msm8917_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0x64,
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x1200, .len = 0x64,
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}, {
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.name = "ctl_2", .id = CTL_2,
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.base = 0x1400, .len = 0x64,
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},
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};
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static const struct dpu_sspp_cfg msm8917_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
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.base = 0x4000, .len = 0x150,
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.features = VIG_MSM8953_MASK,
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.sblk = &dpu_vig_sblk_qseed2,
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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.clk_ctrl = DPU_CLK_CTRL_VIG0,
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}, {
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.name = "sspp_4", .id = SSPP_RGB0,
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.base = 0x14000, .len = 0x150,
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.features = RGB_MSM8953_MASK,
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.sblk = &dpu_rgb_sblk,
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.xin_id = 1,
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.type = SSPP_TYPE_RGB,
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.clk_ctrl = DPU_CLK_CTRL_RGB0,
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}, {
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.name = "sspp_5", .id = SSPP_RGB1,
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.base = 0x16000, .len = 0x150,
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.features = RGB_MSM8953_MASK,
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.sblk = &dpu_rgb_sblk,
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.xin_id = 5,
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.type = SSPP_TYPE_RGB,
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.clk_ctrl = DPU_CLK_CTRL_RGB1,
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}, {
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.name = "sspp_8", .id = SSPP_DMA0,
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.base = 0x24000, .len = 0x150,
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.features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
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.sblk = &dpu_dma_sblk,
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.xin_id = 2,
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.type = SSPP_TYPE_DMA,
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.clk_ctrl = DPU_CLK_CTRL_DMA0,
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},
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};
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static const struct dpu_lm_cfg msm8917_lm[] = {
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{
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.name = "lm_0", .id = LM_0,
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.base = 0x44000, .len = 0x320,
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.sblk = &msm8998_lm_sblk,
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.pingpong = PINGPONG_0,
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.dspp = DSPP_0,
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},
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};
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static const struct dpu_pingpong_cfg msm8917_pp[] = {
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{
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.name = "pingpong_0", .id = PINGPONG_0,
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.base = 0x70000, .len = 0xd4,
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.features = PINGPONG_MSM8996_MASK,
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.sblk = &msm8996_pp_sblk,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
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},
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};
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static const struct dpu_dspp_cfg msm8917_dspp[] = {
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{
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.name = "dspp_0", .id = DSPP_0,
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.base = 0x54000, .len = 0x1800,
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.features = DSPP_SC7180_MASK,
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.sblk = &msm8998_dspp_sblk,
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},
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};
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static const struct dpu_intf_cfg msm8917_intf[] = {
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{
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.name = "intf_1", .id = INTF_1,
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.base = 0x6a800, .len = 0x268,
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.type = INTF_DSI,
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.controller_id = MSM_DSI_CONTROLLER_0,
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.prog_fetch_lines_worst_case = 14,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
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.intr_tear_rd_ptr = -1,
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},
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};
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static const struct dpu_perf_cfg msm8917_perf_data = {
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.max_bw_low = 1800000,
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.max_bw_high = 1800000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 0, /* No LLCC on this SoC */
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.min_dram_ib = 800000,
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.undersized_prefill_lines = 2,
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.xtra_prefill_lines = 2,
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.dest_scale_prefill_lines = 3,
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.macrotile_prefill_lines = 4,
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.yuv_nv12_prefill_lines = 8,
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.linear_prefill_lines = 1,
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.downscaling_prefill_lines = 1,
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.amortizable_threshold = 25,
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.min_prefill_lines = 21,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(msm8998_qos_linear),
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.entries = msm8998_qos_linear
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},
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{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
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.entries = msm8998_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
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.entries = msm8998_qos_nrt
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_version msm8917_mdss_ver = {
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.core_major_ver = 1,
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.core_minor_ver = 15,
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};
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const struct dpu_mdss_cfg dpu_msm8917_cfg = {
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.mdss_ver = &msm8917_mdss_ver,
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.caps = &msm8917_dpu_caps,
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.mdp = msm8917_mdp,
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.ctl_count = ARRAY_SIZE(msm8917_ctl),
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.ctl = msm8917_ctl,
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.sspp_count = ARRAY_SIZE(msm8917_sspp),
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.sspp = msm8917_sspp,
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.mixer_count = ARRAY_SIZE(msm8917_lm),
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.mixer = msm8917_lm,
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.dspp_count = ARRAY_SIZE(msm8917_dspp),
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.dspp = msm8917_dspp,
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.pingpong_count = ARRAY_SIZE(msm8917_pp),
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.pingpong = msm8917_pp,
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.intf_count = ARRAY_SIZE(msm8917_intf),
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.intf = msm8917_intf,
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.vbif_count = ARRAY_SIZE(msm8996_vbif),
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.vbif = msm8996_vbif,
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.perf = &msm8917_perf_data,
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};
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#endif
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@ -780,6 +780,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
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#include "catalog/dpu_1_7_msm8996.h"
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#include "catalog/dpu_1_14_msm8937.h"
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#include "catalog/dpu_1_15_msm8917.h"
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#include "catalog/dpu_1_16_msm8953.h"
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#include "catalog/dpu_3_0_msm8998.h"
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@ -831,6 +831,7 @@ struct dpu_mdss_cfg {
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const struct dpu_format_extended *vig_formats;
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};
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extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
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extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
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extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
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extern const struct dpu_mdss_cfg dpu_msm8996_cfg;
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@ -1445,6 +1445,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
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};
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static const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
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{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
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{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
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{ .compatible = "qcom,msm8996-mdp5", .data = &dpu_msm8996_cfg, },
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@ -983,6 +983,7 @@ module_param(prefer_mdp5, bool, 0444);
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/* list all platforms supported by both mdp5 and dpu drivers */
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static const char *const msm_mdp5_dpu_migration[] = {
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"qcom,msm8917-mdp5",
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"qcom,msm8937-mdp5",
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"qcom,msm8953-mdp5",
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"qcom,msm8996-mdp5",
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