mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-05 20:30:41 +00:00
arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on QDU1000 and QRU1000 SoCs. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230313125731.17745-1-quic_kbajaj@quicinc.com
This commit is contained in:
parent
ec57cbce1a
commit
6209038f13
@ -1321,6 +1321,18 @@ gem_noc: interconnect@19100000 {
|
|||||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||||
#interconnect-cells = <2>;
|
#interconnect-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
system-cache-controller@19200000 {
|
||||||
|
compatible = "qcom,qdu1000-llcc";
|
||||||
|
reg = <0 0x19200000 0 0xd80000>,
|
||||||
|
<0 0x1a200000 0 0x80000>,
|
||||||
|
<0 0x221c8128 0 0x4>;
|
||||||
|
reg-names = "llcc_base",
|
||||||
|
"llcc_broadcast_base",
|
||||||
|
"multi_channel_register";
|
||||||
|
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
multi-ch-bit-off = <24 2>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
timer {
|
timer {
|
||||||
|
Loading…
Reference in New Issue
Block a user