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dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc path

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There's a separate path that allows register access from CPUSS.
Describe it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/641464/
Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-2-0c84aceb0ef9@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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Konrad Dybcio 2025-03-06 19:11:14 +01:00 committed by Dmitry Baryshkov
parent 98a8920e7b
commit 60b8d3a236
1 changed files with 5 additions and 1 deletions
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Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
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@ -38,12 +38,16 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
items:
- description: Interconnect path from the MDP0 port to the data bus
- description: Interconnect path from the MDP1 port to the data bus
- description: Interconnect path from the CPU to the reg bus
interconnect-names:
items:
- const: mdp0-mem
- const: mdp1-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":