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arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration

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The SDM630 SoC features an Adreno 508.0 GPU with a minimum frequency
of 160MHz and a maximum of (depending on the speed-bin) 775MHz.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210728222542.54269-20-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
AngeloGioacchino Del Regno 2021-07-29 00:25:22 +02:00 committed by Bjorn Andersson
parent adc57d4a46
commit 5cf69dcbec
1 changed files with 83 additions and 1 deletions
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84
arch/arm64/boot/dts/qcom/sdm630.dtsi
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@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2020, Konrad Dybcio * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
* Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
*/ */
#include <dt-bindings/clock/qcom,gcc-sdm660.h> #include <dt-bindings/clock/qcom,gcc-sdm660.h>
@ -958,6 +959,87 @@ sd-cd {
}; };
}; };
adreno_gpu: gpu@5000000 {
compatible = "qcom,adreno-508.0", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0x05000000 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gpucc GPUCC_RBBMTIMER_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_GPU_BIMC_GFX_CLK>,
<&gpucc GPUCC_RBCPR_CLK>,
<&gpucc GPUCC_GFX3D_CLK>;
clock-names = "iface",
"rbbmtimer",
"mem",
"mem_iface",
"rbcpr",
"core";
power-domains = <&rpmpd SDM660_VDDMX>;
iommus = <&kgsl_smmu 0>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
interconnects = <&gnoc 1 &bimc 5>;
interconnect-names = "gfx-mem";
operating-points-v2 = <&gpu_sdm630_opp_table>;
gpu_sdm630_opp_table: opp-table {
compatible = "operating-points-v2";
opp-775000000 {
opp-hz = /bits/ 64 <775000000>;
opp-level = <RPM_SMD_LEVEL_TURBO>;
opp-peak-kBps = <5412000>;
opp-supported-hw = <0xA2>;
};
opp-647000000 {
opp-hz = /bits/ 64 <647000000>;
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
opp-peak-kBps = <4068000>;
opp-supported-hw = <0xFF>;
};
opp-588000000 {
opp-hz = /bits/ 64 <588000000>;
opp-level = <RPM_SMD_LEVEL_NOM>;
opp-peak-kBps = <3072000>;
opp-supported-hw = <0xFF>;
};
opp-465000000 {
opp-hz = /bits/ 64 <465000000>;
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
opp-peak-kBps = <2724000>;
opp-supported-hw = <0xFF>;
};
opp-370000000 {
opp-hz = /bits/ 64 <370000000>;
opp-level = <RPM_SMD_LEVEL_SVS>;
opp-peak-kBps = <2188000>;
opp-supported-hw = <0xFF>;
};
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
opp-peak-kBps = <1648000>;
opp-supported-hw = <0xFF>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
opp-peak-kBps = <1200000>;
opp-supported-hw = <0xFF>;
};
};
};
kgsl_smmu: iommu@5040000 { kgsl_smmu: iommu@5040000 {
compatible = "qcom,sdm630-smmu-v2", compatible = "qcom,sdm630-smmu-v2",
"qcom,adreno-smmu", "qcom,smmu-v2"; "qcom,adreno-smmu", "qcom,smmu-v2";