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arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition

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Add CAMSS block definition for sc8280xp.

This drop contains definitions for the following components on sc8280xp:

VFE * 4
VFE Lite * 4
CSID * 4
CSIPHY * 4

This dtsi definition has been developed and validated on a Lenovo X13s
laptop.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-4-cdd5c57ff1dc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Bryan O'Donoghue 2024-01-11 17:15:57 +00:00 committed by Bjorn Andersson
parent 7cfa2e758b
commit 5994dd6075
1 changed files with 235 additions and 0 deletions
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235
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
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@ -3614,6 +3614,241 @@ cci3_i2c1: i2c-bus@1 {
};
};
camss: camss@ac5a000 {
compatible = "qcom,sc8280xp-camss";
reg = <0 0x0ac5a000 0 0x2000>,
<0 0x0ac5c000 0 0x2000>,
<0 0x0ac65000 0 0x2000>,
<0 0x0ac67000 0 0x2000>,
<0 0x0acaf000 0 0x4000>,
<0 0x0acb3000 0 0x1000>,
<0 0x0acb6000 0 0x4000>,
<0 0x0acba000 0 0x1000>,
<0 0x0acbd000 0 0x4000>,
<0 0x0acc1000 0 0x1000>,
<0 0x0acc4000 0 0x4000>,
<0 0x0acc8000 0 0x1000>,
<0 0x0accb000 0 0x4000>,
<0 0x0accf000 0 0x1000>,
<0 0x0acd2000 0 0x4000>,
<0 0x0acd6000 0 0x1000>,
<0 0x0acd9000 0 0x4000>,
<0 0x0acdd000 0 0x1000>,
<0 0x0ace0000 0 0x4000>,
<0 0x0ace4000 0 0x1000>;
reg-names = "csiphy2",
"csiphy3",
"csiphy0",
"csiphy1",
"vfe0",
"csid0",
"vfe1",
"csid1",
"vfe2",
"csid2",
"vfe_lite0",
"csid0_lite",
"vfe_lite1",
"csid1_lite",
"vfe_lite2",
"csid2_lite",
"vfe_lite3",
"csid3_lite",
"vfe3",
"csid3";
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csid1_lite",
"vfe_lite1",
"csiphy3",
"csid0",
"vfe0",
"csid1",
"vfe1",
"csid0_lite",
"vfe_lite0",
"csiphy0",
"csiphy1",
"csiphy2",
"csid2",
"vfe2",
"csid3_lite",
"csid2_lite",
"vfe_lite3",
"vfe_lite2",
"csid3",
"vfe3";
power-domains = <&camcc IFE_0_GDSC>,
<&camcc IFE_1_GDSC>,
<&camcc IFE_2_GDSC>,
<&camcc IFE_3_GDSC>,
<&camcc TITAN_TOP_GDSC>;
power-domain-names = "ife0",
"ife1",
"ife2",
"ife3",
"top";
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_CPAS_AHB_CLK>,
<&camcc CAMCC_CSIPHY0_CLK>,
<&camcc CAMCC_CSI0PHYTIMER_CLK>,
<&camcc CAMCC_CSIPHY1_CLK>,
<&camcc CAMCC_CSI1PHYTIMER_CLK>,
<&camcc CAMCC_CSIPHY2_CLK>,
<&camcc CAMCC_CSI2PHYTIMER_CLK>,
<&camcc CAMCC_CSIPHY3_CLK>,
<&camcc CAMCC_CSI3PHYTIMER_CLK>,
<&camcc CAMCC_IFE_0_AXI_CLK>,
<&camcc CAMCC_IFE_0_CLK>,
<&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_0_CSID_CLK>,
<&camcc CAMCC_IFE_1_AXI_CLK>,
<&camcc CAMCC_IFE_1_CLK>,
<&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_1_CSID_CLK>,
<&camcc CAMCC_IFE_2_AXI_CLK>,
<&camcc CAMCC_IFE_2_CLK>,
<&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_2_CSID_CLK>,
<&camcc CAMCC_IFE_3_AXI_CLK>,
<&camcc CAMCC_IFE_3_CLK>,
<&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_3_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_0_CLK>,
<&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_1_CLK>,
<&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_2_CLK>,
<&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_3_CLK>,
<&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&gcc GCC_CAMERA_SF_AXI_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"csiphy2",
"csiphy2_timer",
"csiphy3",
"csiphy3_timer",
"vfe0_axi",
"vfe0",
"vfe0_cphy_rx",
"vfe0_csid",
"vfe1_axi",
"vfe1",
"vfe1_cphy_rx",
"vfe1_csid",
"vfe2_axi",
"vfe2",
"vfe2_cphy_rx",
"vfe2_csid",
"vfe3_axi",
"vfe3",
"vfe3_cphy_rx",
"vfe3_csid",
"vfe_lite0",
"vfe_lite0_cphy_rx",
"vfe_lite0_csid",
"vfe_lite1",
"vfe_lite1_cphy_rx",
"vfe_lite1_csid",
"vfe_lite2",
"vfe_lite2_cphy_rx",
"vfe_lite2_csid",
"vfe_lite3",
"vfe_lite3_cphy_rx",
"vfe_lite3_csid",
"gcc_axi_hf",
"gcc_axi_sf";
iommus = <&apps_smmu 0x2000 0x4e0>,
<&apps_smmu 0x2020 0x4e0>,
<&apps_smmu 0x2040 0x4e0>,
<&apps_smmu 0x2060 0x4e0>,
<&apps_smmu 0x2080 0x4e0>,
<&apps_smmu 0x20e0 0x4e0>,
<&apps_smmu 0x20c0 0x4e0>,
<&apps_smmu 0x20a0 0x4e0>,
<&apps_smmu 0x2400 0x4e0>,
<&apps_smmu 0x2420 0x4e0>,
<&apps_smmu 0x2440 0x4e0>,
<&apps_smmu 0x2460 0x4e0>,
<&apps_smmu 0x2480 0x4e0>,
<&apps_smmu 0x24e0 0x4e0>,
<&apps_smmu 0x24c0 0x4e0>,
<&apps_smmu 0x24a0 0x4e0>;
interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
<&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
<&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
<&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "cam_ahb",
"cam_hf_mnoc",
"cam_sf_mnoc",
"cam_sf_icp_mnoc";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8280xp-camcc";
reg = <0 0x0ad00000 0 0x20000>;