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drm/xe/xe_guc_ads: save/restore OA registers and allowlist regs

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Several OA registers and allowlist registers were missing from the
save/restore list for GuC and could be lost during an engine reset.  Add
them to the list.

v2:
- Fix commit message (Umesh)
- Add missing closes (Ashutosh)

v3:
- Add missing fixes (Ashutosh)

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2249
Fixes: dd08ebf6c3 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Suggested-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Suggested-by: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: stable@vger.kernel.org # v6.11+
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241023200716.82624-1-jonathan.cavitt@intel.com
This commit is contained in:
Jonathan Cavitt 2024-10-23 20:07:15 +00:00 committed by Ashutosh Dixit
parent 85d3f9e84e
commit 55858fa7eb
1 changed files with 14 additions and 0 deletions
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14
drivers/gpu/drm/xe/xe_guc_ads.c
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@ -15,6 +15,7 @@
#include "regs/xe_engine_regs.h" #include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h" #include "regs/xe_gt_regs.h"
#include "regs/xe_guc_regs.h" #include "regs/xe_guc_regs.h"
#include "regs/xe_oa_regs.h"
#include "xe_bo.h" #include "xe_bo.h"
#include "xe_gt.h" #include "xe_gt.h"
#include "xe_gt_ccs_mode.h" #include "xe_gt_ccs_mode.h"
@ -740,6 +741,11 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
guc_mmio_regset_write_one(ads, regset_map, e->reg, count++); guc_mmio_regset_write_one(ads, regset_map, e->reg, count++);
} }
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
guc_mmio_regset_write_one(ads, regset_map,
RING_FORCE_TO_NONPRIV(hwe->mmio_base, i),
count++);
/* Wa_1607983814 */ /* Wa_1607983814 */
if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) { if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) { for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
@ -748,6 +754,14 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
} }
} }
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL0, count++);
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL1, count++);
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL2, count++);
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL3, count++);
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL4, count++);
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL5, count++);
guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL6, count++);
return count; return count;
} }