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dt-bindings: memory-controller: Define fallback compatible

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All of the DDR controllers beyond revision b.2.1 have had a consistent
layout, therefore define a "brcm,brcmstb-memc-ddr-rev-b.2.1" fallback
compatible string to match them all rather than having to continuously
add to the list.

Link: https://lore.kernel.org/all/20241217194439.929040-2-florian.fainelli@broadcom.com/
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250609212356.2264244-2-florian.fainelli@broadcom.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Florian Fainelli 2025-06-09 14:23:55 -07:00 committed by Krzysztof Kozlowski
parent a0be20055d
commit 501be7cece
1 changed files with 34 additions and 20 deletions
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22
Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml
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@ -11,11 +11,10 @@ maintainers:
properties:
compatible:
oneOf:
- description: Revision > 2.1 controllers
items:
- enum:
- brcm,brcmstb-memc-ddr-rev-b.1.x
- brcm,brcmstb-memc-ddr-rev-b.2.0
- brcm,brcmstb-memc-ddr-rev-b.2.1
- brcm,brcmstb-memc-ddr-rev-b.2.2
- brcm,brcmstb-memc-ddr-rev-b.2.3
- brcm,brcmstb-memc-ddr-rev-b.2.5
@ -29,6 +28,19 @@ properties:
- brcm,brcmstb-memc-ddr-rev-c.1.2
- brcm,brcmstb-memc-ddr-rev-c.1.3
- brcm,brcmstb-memc-ddr-rev-c.1.4
- const: brcm,brcmstb-memc-ddr-rev-b.2.1
- const: brcm,brcmstb-memc-ddr
- description: Revision 2.1 controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.2.1
- const: brcm,brcmstb-memc-ddr
- description: Revision 2.0 controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.2.0
- const: brcm,brcmstb-memc-ddr
- description: Revision 1.x controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.1.x
- const: brcm,brcmstb-memc-ddr
reg:
@ -46,7 +58,9 @@ additionalProperties: false
examples:
- |
memory-controller@9902000 {
compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
"brcm,brcmstb-memc-ddr-rev-b.2.1",
"brcm,brcmstb-memc-ddr";
reg = <0x9902000 0x600>;
clock-frequency = <2133000000>;
};