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arm64: dts: qcom: x1e80100: Add USB nodes
Add nodes for all USB controllers and their PHYs for X1E80100 platform. Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-6-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa
Bjorn Andersson
parent
8b6e2bf94b
commit
4af46b7bd6
@ -5,11 +5,13 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
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#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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@ -742,9 +744,9 @@ gcc: clock-controller@100000 {
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>;
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<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
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<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
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<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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@ -2500,6 +2502,126 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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};
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};
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usb_1_ss0_hsphy: phy@fd3000 {
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compatible = "qcom,x1e80100-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x00fd3000 0 0x154>;
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#phy-cells = <0>;
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clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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status = "disabled";
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};
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usb_1_ss0_qmpphy: phy@fd5000 {
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compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
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reg = <0 0x00fd5000 0 0x4000>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"usb3_pipe";
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power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <1>;
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#phy-cells = <1>;
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status = "disabled";
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};
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usb_1_ss1_hsphy: phy@fd9000 {
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compatible = "qcom,x1e80100-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x00fd9000 0 0x154>;
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#phy-cells = <0>;
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clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
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status = "disabled";
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};
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usb_1_ss1_qmpphy: phy@fda000 {
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compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
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reg = <0 0x00fda000 0 0x4000>;
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"usb3_pipe";
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power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
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resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
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<&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <1>;
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#phy-cells = <1>;
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status = "disabled";
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};
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usb_1_ss2_hsphy: phy@fde000 {
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compatible = "qcom,x1e80100-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x00fde000 0 0x154>;
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#phy-cells = <0>;
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clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
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status = "disabled";
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};
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usb_1_ss2_qmpphy: phy@fdf000 {
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compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
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reg = <0 0x00fdf000 0 0x4000>;
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clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"usb3_pipe";
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power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
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resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
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<&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
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reset-names = "phy",
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"common";
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#clock-cells = <1>;
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#phy-cells = <1>;
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status = "disabled";
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};
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cnoc_main: interconnect@1500000 {
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compatible = "qcom,x1e80100-cnoc-main";
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reg = <0 0x1500000 0 0x14400>;
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@ -2667,6 +2789,331 @@ lpass_lpicx_noc: interconnect@7430000 {
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#interconnect-cells = <2>;
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};
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usb_2_hsphy: phy@88e0000 {
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compatible = "qcom,x1e80100-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x088e0000 0 0x154>;
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#phy-cells = <0>;
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clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
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status = "disabled";
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};
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usb_1_ss2: usb@a0f8800 {
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compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
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reg = <0 0x0a0f8800 0 0x400>;
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clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
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<&gcc GCC_USB30_TERT_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
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<&gcc GCC_USB30_TERT_SLEEP_CLK>,
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<&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
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"noc_aggr",
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"noc_aggr_north",
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"noc_aggr_south",
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"noc_sys";
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assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_TERT_MASTER_CLK>;
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assigned-clock-rates = <19200000>,
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<200000000>;
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interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 58 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 57 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq",
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"ss_phy_irq";
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power-domains = <&gcc GCC_USB30_TERT_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB30_TERT_BCR>;
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interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "usb-ddr",
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"apps-usb";
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wakeup-source;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb_1_ss2_dwc3: usb@a000000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a000000 0 0xcd00>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x14a0 0x0>;
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phys = <&usb_1_ss2_hsphy>,
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<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
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phy-names = "usb2-phy",
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"usb3-phy";
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,usb3_lpm_capable;
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dma-coherent;
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port {
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usb_1_ss2_role_switch: endpoint {
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};
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};
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};
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};
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usb_2: usb@a2f8800 {
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compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
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reg = <0 0x0a2f8800 0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_USB20_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_USB20_SLEEP_CLK>,
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<&gcc GCC_USB20_MOCK_UTMI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
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"noc_aggr",
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"noc_aggr_north",
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"noc_aggr_south",
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"noc_sys";
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assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
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<&gcc GCC_USB20_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 50 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 49 IRQ_TYPE_EDGE_BOTH>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq";
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power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB20_PRIM_BCR>;
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interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "usb-ddr",
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"apps-usb";
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wakeup-source;
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status = "disabled";
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usb_2_dwc3: usb@a200000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a200000 0 0xcd00>;
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interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x14e0 0x0>;
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phys = <&usb_2_hsphy>;
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phy-names = "usb2-phy";
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maximum-speed = "high-speed";
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port {
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usb_2_role_switch: endpoint {
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};
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};
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};
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};
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usb_1_ss0: usb@a6f8800 {
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compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
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reg = <0 0x0a6f8800 0 0x400>;
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
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<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
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"noc_aggr",
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"noc_aggr_north",
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"noc_aggr_south",
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"noc_sys";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>,
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<200000000>;
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interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 61 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq",
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"ss_phy_irq";
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power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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wakeup-source;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb_1_ss0_dwc3: usb@a600000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a600000 0 0xcd00>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x1420 0x0>;
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phys = <&usb_1_ss0_hsphy>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
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phy-names = "usb2-phy",
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"usb3-phy";
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,usb3_lpm_capable;
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dma-coherent;
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port {
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usb_1_ss0_role_switch: endpoint {
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};
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};
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};
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};
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usb_1_ss1: usb@a8f8800 {
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compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
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reg = <0 0x0a8f8800 0 0x400>;
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clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_SLEEP_CLK>,
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<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
|
||||
"mock_utmi",
|
||||
"noc_aggr",
|
||||
"noc_aggr_north",
|
||||
"noc_aggr_south",
|
||||
"noc_sys";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>,
|
||||
<200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 60 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq",
|
||||
"ss_phy_irq";
|
||||
|
||||
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
|
||||
interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "usb-ddr",
|
||||
"apps-usb";
|
||||
|
||||
wakeup-source;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
usb_1_ss1_dwc3: usb@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xcd00>;
|
||||
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
iommus = <&apps_smmu 0x1460 0x0>;
|
||||
|
||||
phys = <&usb_1_ss1_hsphy>,
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
|
||||
phy-names = "usb2-phy",
|
||||
"usb3-phy";
|
||||
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,usb3_lpm_capable;
|
||||
|
||||
dma-coherent;
|
||||
|
||||
port {
|
||||
usb_1_ss1_role_switch: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
|
||||
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user