Proxmox-Port/linux-loongson
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson synced 2025-08-27 15:36:48 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

riscv: misaligned: enable IRQs while handling misaligned accesses

Browse Source 
We can safely reenable IRQs if coming from userspace. This allows to
access user memory that could potentially trigger a page fault.

Fixes: b686ecdeac ("riscv: misaligned: Restrict user access to kernel memory")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250422162324.956065-3-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
This commit is contained in:
Clément Léger 2025-04-22 18:23:09 +02:00 committed by Alexandre Ghiti
parent fd94de9f9e
commit 453805f0a2
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/kernel/traps.c
View File

@ -220,20 +220,24 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type
{ {
irqentry_state_t state; irqentry_state_t state;
if (user_mode(regs)) if (user_mode(regs)) {
irqentry_enter_from_user_mode(regs); irqentry_enter_from_user_mode(regs);
else local_irq_enable();
} else {
state = irqentry_nmi_enter(regs); state = irqentry_nmi_enter(regs);
}
if (misaligned_handler[type].handler(regs)) if (misaligned_handler[type].handler(regs))
do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
misaligned_handler[type].type_str); misaligned_handler[type].type_str);
if (user_mode(regs)) if (user_mode(regs)) {
local_irq_disable();
irqentry_exit_to_user_mode(regs); irqentry_exit_to_user_mode(regs);
else } else {
irqentry_nmi_exit(regs, state); irqentry_nmi_exit(regs, state);
} }
}
asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs) asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
{ {