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drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards

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In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.

We don't need to set the CFF bit as selective update configuration in
PSR2_MAN_TRL_CTL is not overwritten anymore. I.e. we have valid
configuration in PSR2_MAN_TRK_CTL and in plane SEL_FETCH_* registers when
SFF bit gets cleared by the HW in case something triggers "frame change"
event after SFF bit is cleared.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-6-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander 2025-02-13 08:47:56 +02:00
parent 3b5bf853e3
commit 411ad63877
1 changed files with 15 additions and 7 deletions
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22
drivers/gpu/drm/i915/display/intel_psr.c
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@ -2359,7 +2359,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
lockdep_assert_held(&intel_dp->psr.lock);
if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
return;
break;
}
@ -3130,12 +3130,16 @@ static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)
if (!intel_dp->psr.psr2_sel_fetch_enabled)
return;
intel_de_write(display,
PSR2_MAN_TRK_CTL(display, cpu_transcoder),
man_trk_ctl_enable_bit_get(display) |
man_trk_ctl_partial_frame_bit_get(display) |
man_trk_ctl_single_full_frame_bit_get(display) |
man_trk_ctl_continuos_full_frame(display));
if (DISPLAY_VER(display) >= 20)
intel_de_write(display, LNL_SFF_CTL(cpu_transcoder),
LNL_SFF_CTL_SF_SINGLE_FULL_FRAME);
else
intel_de_write(display,
PSR2_MAN_TRK_CTL(display, cpu_transcoder),
man_trk_ctl_enable_bit_get(display) |
man_trk_ctl_partial_frame_bit_get(display) |
man_trk_ctl_single_full_frame_bit_get(display) |
man_trk_ctl_continuos_full_frame(display));
}
static void _psr_invalidate_handle(struct intel_dp *intel_dp)
@ -3239,6 +3243,10 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
* Still keep cff bit enabled as we don't have proper SU
* configuration in case update is sent for any reason after
* sff bit gets cleared by the HW on next vblank.
*
* NOTE: Setting cff bit is not needed for LunarLake onwards as
* we have own register for SFF bit and we are not overwriting
* existing SU configuration
*/
intel_psr_configure_full_frame_update(intel_dp);
}