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drm/xe: Make WA BB part of LRC BO
No idea why, but without this GuC context switches randomly fail when
running IGTs in a loop. Need to follow up why this fixes the
aforementioned issue but can live with a stable driver for now.
Fixes: 617d824c53
("drm/xe: Add WA BB to capture active context utilization")
Cc: stable@vger.kernel.org
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Tested-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://lore.kernel.org/r/20250612031925.4009701-1-matthew.brost@intel.com
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@ -40,6 +40,7 @@
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#define LRC_PPHWSP_SIZE SZ_4K
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#define LRC_INDIRECT_RING_STATE_SIZE SZ_4K
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#define LRC_WA_BB_SIZE SZ_4K
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static struct xe_device *
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lrc_to_xe(struct xe_lrc *lrc)
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@ -910,7 +911,6 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
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{
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xe_hw_fence_ctx_finish(&lrc->fence_ctx);
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xe_bo_unpin_map_no_vm(lrc->bo);
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xe_bo_unpin_map_no_vm(lrc->bb_per_ctx_bo);
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}
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/*
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@ -973,22 +973,27 @@ struct wa_bb_setup {
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u32 *batch, size_t max_size);
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};
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static size_t wa_bb_offset(struct xe_lrc *lrc)
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{
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return lrc->bo->size - LRC_WA_BB_SIZE;
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}
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static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
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{
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const size_t max_size = lrc->bb_per_ctx_bo->size;
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const size_t max_size = LRC_WA_BB_SIZE;
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static const struct wa_bb_setup funcs[] = {
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{ .setup = wa_bb_setup_utilization },
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};
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ssize_t remain;
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u32 *cmd, *buf = NULL;
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if (lrc->bb_per_ctx_bo->vmap.is_iomem) {
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if (lrc->bo->vmap.is_iomem) {
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buf = kmalloc(max_size, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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cmd = buf;
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} else {
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cmd = lrc->bb_per_ctx_bo->vmap.vaddr;
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cmd = lrc->bo->vmap.vaddr + wa_bb_offset(lrc);
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}
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remain = max_size / sizeof(*cmd);
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@ -1011,13 +1016,14 @@ static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
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*cmd++ = MI_BATCH_BUFFER_END;
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if (buf) {
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xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bb_per_ctx_bo->vmap, 0,
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buf, (cmd - buf) * sizeof(*cmd));
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xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bo->vmap,
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wa_bb_offset(lrc), buf,
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(cmd - buf) * sizeof(*cmd));
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kfree(buf);
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}
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xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR,
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xe_bo_ggtt_addr(lrc->bb_per_ctx_bo) | 1);
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xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR, xe_bo_ggtt_addr(lrc->bo) +
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wa_bb_offset(lrc) + 1);
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return 0;
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@ -1059,20 +1065,13 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
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* FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
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* via VM bind calls.
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*/
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lrc->bo = xe_bo_create_pin_map(xe, tile, NULL, lrc_size,
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lrc->bo = xe_bo_create_pin_map(xe, tile, NULL,
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lrc_size + LRC_WA_BB_SIZE,
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ttm_bo_type_kernel,
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bo_flags);
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if (IS_ERR(lrc->bo))
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return PTR_ERR(lrc->bo);
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lrc->bb_per_ctx_bo = xe_bo_create_pin_map(xe, tile, NULL, SZ_4K,
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ttm_bo_type_kernel,
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bo_flags);
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if (IS_ERR(lrc->bb_per_ctx_bo)) {
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err = PTR_ERR(lrc->bb_per_ctx_bo);
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goto err_lrc_finish;
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}
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lrc->size = lrc_size;
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lrc->ring.size = ring_size;
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lrc->ring.tail = 0;
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@ -1860,7 +1859,8 @@ struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc)
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snapshot->seqno = xe_lrc_seqno(lrc);
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snapshot->lrc_bo = xe_bo_get(lrc->bo);
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snapshot->lrc_offset = xe_lrc_pphwsp_offset(lrc);
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snapshot->lrc_size = lrc->bo->size - snapshot->lrc_offset;
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snapshot->lrc_size = lrc->bo->size - snapshot->lrc_offset -
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LRC_WA_BB_SIZE;
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snapshot->lrc_snapshot = NULL;
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snapshot->ctx_timestamp = lower_32_bits(xe_lrc_ctx_timestamp(lrc));
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snapshot->ctx_job_timestamp = xe_lrc_ctx_job_timestamp(lrc);
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@ -53,9 +53,6 @@ struct xe_lrc {
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/** @ctx_timestamp: readout value of CTX_TIMESTAMP on last update */
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u64 ctx_timestamp;
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/** @bb_per_ctx_bo: buffer object for per context batch wa buffer */
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struct xe_bo *bb_per_ctx_bo;
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};
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struct xe_lrc_snapshot;
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