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arm64: dts: mt7622: add mmc related device nodes

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add mmc device nodes and proper setup for used pins

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Jimin Wang <jimin.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Sean Wang 2018-02-18 03:54:50 +08:00 committed by Matthias Brugger
parent 0f12d5b3c7
commit 2c002a3049
2 changed files with 126 additions and 0 deletions
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106
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -8,6 +8,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7622.dtsi" #include "mt7622.dtsi"
#include "mt6380.dtsi" #include "mt6380.dtsi"
@ -53,6 +54,14 @@ memory {
reg = <0 0x40000000 0 0x3F000000>; reg = <0 0x40000000 0 0x3F000000>;
}; };
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v { reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "fixed-3.3V"; regulator-name = "fixed-3.3V";
@ -89,6 +98,23 @@ mux {
function = "emmc", "emmc_rst"; function = "emmc", "emmc_rst";
groups = "emmc"; groups = "emmc";
}; };
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
*/
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
}; };
emmc_pins_uhs: emmc-pins-uhs { emmc_pins_uhs: emmc-pins-uhs {
@ -96,6 +122,21 @@ mux {
function = "emmc"; function = "emmc";
groups = "emmc"; groups = "emmc";
}; };
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
drive-strength = <4>;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
drive-strength = <4>;
bias-pull-down;
};
}; };
eth_pins: eth-pins { eth_pins: eth-pins {
@ -194,6 +235,27 @@ mux {
function = "sd"; function = "sd";
groups = "sd_0"; groups = "sd_0";
}; };
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
* DAT2, DAT3, CMD, CLK for SD respectively.
*/
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
drive-strength = <8>;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
drive-strength = <12>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
}; };
sd0_pins_uhs: sd0-pins-uhs { sd0_pins_uhs: sd0-pins-uhs {
@ -201,6 +263,18 @@ mux {
function = "sd"; function = "sd";
groups = "sd_0"; groups = "sd_0";
}; };
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
bias-pull-down;
};
}; };
/* Serial NAND is shared pin with SPI-NOR */ /* Serial NAND is shared pin with SPI-NOR */
@ -311,6 +385,38 @@ &i2c2 {
status = "okay"; status = "okay";
}; };
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc { &nandc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>; pinctrl-0 = <&parallel_nand_pins>;

20
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@ -527,6 +527,26 @@ uart4: serial@11019000 {
status = "disabled"; status = "disabled";
}; };
mmc0: mmc@11230000 {
compatible = "mediatek,mt7622-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
<&topckgen CLK_TOP_MSDC50_0_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt7622-mmc";
reg = <0 0x11240000 0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
ssusbsys: ssusbsys@1a000000 { ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", compatible = "mediatek,mt7622-ssusbsys",
"syscon"; "syscon";