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arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card

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Add nodes for eMMC and SD card on sc7280.

Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1626159971-22519-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Shaik Sajida Bhanu 2021-07-13 12:36:11 +05:30 committed by Bjorn Andersson
parent 12dd4ebda4
commit 298c81a7d4
2 changed files with 257 additions and 0 deletions
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71
arch/arm64/boot/dts/qcom/sc7280-idp.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
@ -272,6 +273,34 @@ &qupv3_id_0 {
status = "okay";
};
&sdhc_1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
non-removable;
no-sd;
no-sdio;
vmmc-supply = <&vreg_l7b_2p9>;
vqmmc-supply = <&vreg_l19b_1p8>;
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
vmmc-supply = <&vreg_l9c_2p9>;
vqmmc-supply = <&vreg_l6c_2p9>;
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
};
&uart5 {
status = "okay";
};
@ -291,3 +320,45 @@ rx {
bias-pull-up;
};
};
&sdc1_on {
clk {
bias-disable;
drive-strength = <16>;
};
cmd {
bias-pull-up;
drive-strength = <10>;
};
data {
bias-pull-up;
drive-strength = <10>;
};
rclk {
bias-pull-down;
};
};
&sdc2_on {
clk {
bias-disable;
drive-strength = <16>;
};
cmd {
bias-pull-up;
drive-strength = <10>;
};
data {
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
bias-pull-up;
};
};

186
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@ -24,6 +25,11 @@ / {
chosen { };
aliases {
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
@ -436,6 +442,60 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
status = "disabled";
reg = <0 0x007c4000 0 0x1000>,
<0 0x007c5000 0 0x1000>;
reg-names = "hc", "cqhci";
iommus = <&apps_smmu 0xc0 0x0>;
interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&sdhc1_opp_table>;
bus-width = <8>;
supports-cqe;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1800000 400000>;
opp-avg-kBps = <100000 0>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 1600000>;
opp-avg-kBps = <390000 0>;
};
};
};
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
@ -1035,6 +1095,51 @@ apss_merge_funnel_in: endpoint {
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
status = "disabled";
reg = <0 0x08804000 0 0x1000>;
iommus = <&apps_smmu 0x100 0x0>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
qcom,dll-config = <0x0007642c>;
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1800000 400000>;
opp-avg-kBps = <100000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 1600000>;
opp-avg-kBps = <200000 0>;
};
};
};
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@ -1185,6 +1290,87 @@ qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
};
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
};
cmd {
pins = "sdc1_cmd";
};
data {
pins = "sdc1_data";
};
rclk {
pins = "sdc1_rclk";
};
};
sdc1_off: sdc1-off {
clk {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
cmd {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
data {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
rclk {
pins = "sdc1_rclk";
bias-bus-hold;
};
};
sdc2_on: sdc2-on {
clk {
pins = "sdc2_clk";
};
cmd {
pins = "sdc2_cmd";
};
data {
pins = "sdc2_data";
};
sd-cd {
pins = "gpio91";
};
};
sdc2_off: sdc2-off {
clk {
pins = "sdc2_clk";
drive-strength = <2>;
bias-bus-hold;
};
cmd {
pins ="sdc2_cmd";
drive-strength = <2>;
bias-bus-hold;
};
data {
pins ="sdc2_data";
drive-strength = <2>;
bias-bus-hold;
};
};
};
apps_smmu: iommu@15000000 {