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arm64: dts: qcom: msm8996: Use generic QMP driver for UFS

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With support for the MSM8996 UFS PHY added to the common QMP driver,
migrate the DTS to use the common QMP binding.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200125001234.435384-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Bjorn Andersson 2020-01-24 16:12:34 -08:00
parent 950d3fb6fb
commit 27520210e8
2 changed files with 17 additions and 14 deletions
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6
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View File

@ -999,13 +999,7 @@ &ufsphy {
vdda-phy-supply = <&vreg_l28a_0p925>; vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>; vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&vreg_l25a_1p2>; vddp-ref-clk-supply = <&vreg_l25a_1p2>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
}; };
&ufshc { &ufshc {

25
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -886,7 +886,7 @@ ufshc: ufshc@624000 {
reg = <0x00624000 0x2500>; reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy>; phys = <&ufsphy_lane>;
phy-names = "ufsphy"; phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>; power-domains = <&gcc UFS_GDSC>;
@ -938,16 +938,25 @@ ufs_variant {
}; };
ufsphy: phy@627000 { ufsphy: phy@627000 {
compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; compatible = "qcom,msm8996-qmp-ufs-phy";
reg = <0x00627000 0xda8>; reg = <0x00627000 0x1c4>;
reg-names = "phy_mem"; #address-cells = <1>;
#phy-cells = <0>; #size-cells = <1>;
ranges;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
resets = <&ufshc 0>; resets = <&ufshc 0>;
reset-names = "ufsphy";
status = "disabled"; status = "disabled";
ufsphy_lane: lanes@627400 {
reg = <0x627400 0x12c>,
<0x627600 0x200>,
<0x627c00 0x1b4>;
#phy-cells = <0>;
};
}; };
camss: camss@a00000 { camss: camss@a00000 {