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arm64: dts: qcom: sm8250: remove mmcx regulator

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Switch dispcc and videocc into using MMCX domain directly. Drop the now
unused mmcx regulator.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210829154757.784699-7-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2021-08-29 18:47:55 +03:00 committed by Bjorn Andersson
parent dfe28877db
commit 266e5cf39a
1 changed files with 4 additions and 9 deletions
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13
arch/arm64/boot/dts/qcom/sm8250.dtsi
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@ -272,13 +272,6 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>; reg = <0x0 0x80000000 0x0 0x0>;
}; };
mmcx_reg: mmcx-reg {
compatible = "regulator-fixed-domain";
power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
regulator-name = "MMCX";
};
pmu { pmu {
compatible = "arm,armv8-pmuv3"; compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@ -2571,7 +2564,8 @@ videocc: clock-controller@abf0000 {
clocks = <&gcc GCC_VIDEO_AHB_CLK>, clocks = <&gcc GCC_VIDEO_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>; <&rpmhcc RPMH_CXO_CLK_A>;
mmcx-supply = <&mmcx_reg>; power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
@ -2845,7 +2839,8 @@ opp-358000000 {
dispcc: clock-controller@af00000 { dispcc: clock-controller@af00000 {
compatible = "qcom,sm8250-dispcc"; compatible = "qcom,sm8250-dispcc";
reg = <0 0x0af00000 0 0x10000>; reg = <0 0x0af00000 0 0x10000>;
mmcx-supply = <&mmcx_reg>; power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
clocks = <&rpmhcc RPMH_CXO_CLK>, clocks = <&rpmhcc RPMH_CXO_CLK>,
<&dsi0_phy 0>, <&dsi0_phy 0>,
<&dsi0_phy 1>, <&dsi0_phy 1>,