Proxmox-Port/linux-loongson
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson synced 2025-09-06 13:09:58 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters

Browse Source 
SM8250 has TX and RX macros with SoundWire Controllers to attach with
codecs like WCD938x. Add these nodes for sm8250 mtp audio use case.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211006164712.16078-2-srinivas.kandagatla@linaro.org
This commit is contained in:
Srinivas Kandagatla 2021-10-06 17:47:09 +01:00 committed by Bjorn Andersson
parent fa55b7dcdc
commit 24f52ef0c4
1 changed files with 157 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

157
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -1831,6 +1831,101 @@ vamacro: codec@3370000 {
#sound-dai-cells = <1>; #sound-dai-cells = <1>;
}; };
rxmacro: rxmacro@3200000 {
pinctrl-names = "default";
pinctrl-0 = <&rx_swr_active>;
compatible = "qcom,sm8250-lpass-rx-macro";
reg = <0 0x3200000 0 0x1000>;
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
#clock-cells = <0>;
clock-frequency = <9600000>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr1: soundwire-controller@3210000 {
reg = <0 0x3210000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rxmacro>;
clock-names = "iface";
label = "RX";
qcom,din-ports = <0>;
qcom,dout-ports = <5>;
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
#sound-dai-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
};
txmacro: txmacro@3220000 {
pinctrl-names = "default";
pinctrl-0 = <&tx_swr_active>;
compatible = "qcom,sm8250-lpass-tx-macro";
reg = <0 0x3220000 0 0x1000>;
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
#clock-cells = <0>;
clock-frequency = <9600000>;
clock-output-names = "mclk";
#address-cells = <2>;
#size-cells = <2>;
#sound-dai-cells = <1>;
};
/* tx macro */
swr2: soundwire-controller@3230000 {
reg = <0 0x3230000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core";
clocks = <&txmacro>;
clock-names = "iface";
label = "TX";
qcom,din-ports = <5>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
qcom,port-offset = <1>;
#sound-dai-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
};
aoncc: clock-controller@3380000 { aoncc: clock-controller@3380000 {
compatible = "qcom,sm8250-lpass-aoncc"; compatible = "qcom,sm8250-lpass-aoncc";
reg = <0 0x03380000 0 0x40000>; reg = <0 0x03380000 0 0x40000>;
@ -1923,6 +2018,68 @@ data {
input-enable; input-enable;
}; };
}; };
rx_swr_active: rx_swr-active-pins {
clk {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
tx_swr_active: tx_swr-active-pins {
clk {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data {
pins = "gpio1", "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
tx_swr_sleep: tx_swr-sleep-pins {
clk {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
input-enable;
bias-pull-down;
};
data1 {
pins = "gpio1";
function = "swr_tx_data";
drive-strength = <2>;
input-enable;
bias-bus-hold;
};
data2 {
pins = "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
input-enable;
bias-pull-down;
};
};
}; };
gpu: gpu@3d00000 { gpu: gpu@3d00000 {