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arm64: dts: qcom: msm8916: specify per-sensor calibration cells

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Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-17-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2023-01-01 21:40:30 +02:00 committed by Bjorn Andersson
parent 0b3aa9aa62
commit 24aafd041f
1 changed files with 79 additions and 6 deletions
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85
arch/arm64/boot/dts/qcom/msm8916.dtsi
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@ -442,11 +442,70 @@ qfprom: qfprom@5c000 {
reg = <0x0005c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tsens_caldata: caldata@d0 {
reg = <0xd0 0x8>;
tsens_base1: base1@d0 {
reg = <0xd0 0x1>;
bits = <0 7>;
};
tsens_calsel: calsel@ec {
reg = <0xec 0x4>;
tsens_s0_p1: s0-p1@d0 {
reg = <0xd0 0x2>;
bits = <7 5>;
};
tsens_s0_p2: s0-p2@d1 {
reg = <0xd1 0x2>;
bits = <4 5>;
};
tsens_s1_p1: s1-p1@d2 {
reg = <0xd2 0x1>;
bits = <1 5>;
};
tsens_s1_p2: s1-p2@d2 {
reg = <0xd2 0x2>;
bits = <6 5>;
};
tsens_s2_p1: s2-p1@d3 {
reg = <0xd3 0x1>;
bits = <3 5>;
};
tsens_s2_p2: s2-p2@d4 {
reg = <0xd4 0x1>;
bits = <0 5>;
};
// no tsens with hw_id 3
tsens_s4_p1: s4-p1@d4 {
reg = <0xd4 0x2>;
bits = <5 5>;
};
tsens_s4_p2: s4-p2@d5 {
reg = <0xd5 0x1>;
bits = <2 5>;
};
tsens_s5_p1: s5-p1@d5 {
reg = <0xd5 0x2>;
bits = <7 5>;
};
tsens_s5_p2: s5-p2@d6 {
reg = <0xd6 0x2>;
bits = <4 5>;
};
tsens_base2: base2@d7 {
reg = <0xd7 0x1>;
bits = <1 7>;
};
tsens_mode: mode@ec {
reg = <0xef 0x1>;
bits = <5 3>;
};
};
@ -473,8 +532,22 @@ tsens: thermal-sensor@4a9000 {
compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
nvmem-cell-names = "calib", "calib_sel";
// no hw_id 3
nvmem-cells = <&tsens_mode>,
<&tsens_base1>, <&tsens_base2>,
<&tsens_s0_p1>, <&tsens_s0_p2>,
<&tsens_s1_p1>, <&tsens_s1_p2>,
<&tsens_s2_p1>, <&tsens_s2_p2>,
<&tsens_s4_p1>, <&tsens_s4_p2>,
<&tsens_s5_p1>, <&tsens_s5_p2>;
nvmem-cell-names = "mode",
"base1", "base2",
"s0_p1", "s0_p2",
"s1_p1", "s1_p2",
"s2_p1", "s2_p2",
"s4_p1", "s4_p2",
"s5_p1", "s5_p2";
#qcom,sensors = <5>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";