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arm64: dts: qcom: sm8250: Add remoteprocs
Add remoteproc nodes for the audio, compute and sensor cores, define glink for each one and enable them on the MTP with appropriate firmware defined. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200622222747.717306-6-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -55,6 +55,11 @@ vreg_s6c_0p88: smpc6-regulator {
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};
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};
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};
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};
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&adsp {
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status = "okay";
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firmware-name = "qcom/sm8250/adsp.mbn";
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};
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&apps_rsc {
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&apps_rsc {
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pm8150-rpmh-regulators {
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pm8150-rpmh-regulators {
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compatible = "qcom,pm8150-rpmh-regulators";
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compatible = "qcom,pm8150-rpmh-regulators";
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@ -348,10 +353,20 @@ vreg_l7f_1p8: ldo7 {
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};
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};
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};
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};
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&cdsp {
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status = "okay";
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firmware-name = "qcom/sm8250/cdsp.mbn";
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};
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&qupv3_id_1 {
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&qupv3_id_1 {
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status = "okay";
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status = "okay";
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};
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};
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&slpi {
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status = "okay";
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firmware-name = "qcom/sm8250/slpi.mbn";
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};
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&tlmm {
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&tlmm {
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gpio-reserved-ranges = <28 4>, <40 4>;
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gpio-reserved-ranges = <28 4>, <40 4>;
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};
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};
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@ -1052,6 +1052,83 @@ tcsr_mutex_regs: syscon@1f40000 {
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reg = <0x0 0x01f40000 0x0 0x40000>;
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reg = <0x0 0x01f40000 0x0 0x40000>;
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};
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};
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slpi: remoteproc@5c00000 {
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compatible = "qcom,sm8250-slpi-pas";
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reg = <0 0x05c00000 0 0x4000>;
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interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
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<&rpmhpd SM8250_LCX>,
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<&rpmhpd SM8250_LMX>;
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power-domain-names = "load_state", "lcx", "lmx";
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memory-region = <&slpi_mem>;
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qcom,smem-states = <&smp2p_slpi_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "lpass";
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qcom,remote-pid = <3>;
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};
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};
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cdsp: remoteproc@8300000 {
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compatible = "qcom,sm8250-cdsp-pas";
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reg = <0 0x08300000 0 0x10000>;
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interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
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<&rpmhpd SM8250_CX>;
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power-domain-names = "load_state", "cx";
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memory-region = <&cdsp_mem>;
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qcom,smem-states = <&smp2p_cdsp_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "lpass";
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qcom,remote-pid = <5>;
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};
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};
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pdc: interrupt-controller@b220000 {
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8250-pdc", "qcom,pdc";
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compatible = "qcom,sm8250-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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@ -1668,6 +1745,45 @@ config {
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};
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};
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};
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};
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adsp: remoteproc@17300000 {
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compatible = "qcom,sm8250-adsp-pas";
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reg = <0 0x17300000 0 0x100>;
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interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
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<&rpmhpd SM8250_LCX>,
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<&rpmhpd SM8250_LMX>;
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power-domain-names = "load_state", "lcx", "lmx";
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memory-region = <&adsp_mem>;
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qcom,smem-states = <&smp2p_adsp_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "lpass";
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qcom,remote-pid = <2>;
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};
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};
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intc: interrupt-controller@17a00000 {
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#interrupt-cells = <3>;
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