mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
arm64: dts: add description for solidrun cn9130 som and clearfog boards
Add description for the SolidRun CN9130 SoM, and Clearfog Base / Pro reference boards. The SoM has been designed as a pin-compatible replacement for the older Armada 388 based SoM. Therefore it supports the same boards and a similar feature set. Most notable upgrades: - 4x Cortex-A72 - 10Gbps SFP - Both eMMC and SD supported at the same time The developer first supporting this product at SolidRun decided to use different filenames for the DTBs: Armada 388 uses the full "clearfog" string while cn9130 uses the abbreviation "cf". This name is already hard-coded in pre-installed vendor u-boot and can not be changed easily. NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE: CN9130 SoM has a different footprint from Armada 388 SoM. Components on the carrier board below the SoM may collide causing damage, such as on Clearfog Base. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Josua Mayer
Gregory CLEMENT
parent
099e1d034f
commit
1c510c7d82
@ -28,3 +28,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
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178
arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
Normal file
178
arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
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@ -0,0 +1,178 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
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*
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* DTS for SolidRun CN9130 Clearfog Base.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "cn9130.dtsi"
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#include "cn9130-sr-som.dtsi"
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#include "cn9130-cf.dtsi"
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/ {
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model = "SolidRun CN9130 Clearfog Base";
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compatible = "solidrun,cn9130-clearfog-base",
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"solidrun,cn9130-sr-som", "marvell,cn9130";
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button-0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&cp0_gpio1 31 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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rfkill-m2-gnss {
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compatible = "rfkill-gpio";
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label = "m.2 GNSS";
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radio-type = "gps";
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&expander0 9 GPIO_ACTIVE_HIGH>;
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};
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/* M.2 is B-keyed, so w-disable is for WWAN */
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rfkill-m2-wwan {
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compatible = "rfkill-gpio";
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label = "m.2 WWAN";
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radio-type = "wwan";
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
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};
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};
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/* SRDS #3 - SGMII 1GE */
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&cp0_eth1 {
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phy = <&phy1>;
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phys = <&cp0_comphy3 1>;
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phy-mode = "sgmii";
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status = "okay";
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};
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&cp0_eth2_phy {
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/*
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* Configure LEDs default behaviour:
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* - LED[0]: link/activity: On/blink (green)
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* - LED[1]: link is 100/1000Mbps: On (yellow)
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* - LED[2]: high impedance (floating)
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*/
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marvell,reg-init = <3 16 0xf000 0x0a61>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_WAN;
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default-state = "keep";
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};
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};
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};
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&cp0_gpio1 {
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sim-select-hog {
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gpio-hog;
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gpios = <27 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "sim-select";
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};
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};
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&cp0_mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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/*
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* Configure LEDs default behaviour:
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* - LED[0]: link/activity: On/blink (green)
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* - LED[1]: link is 100/1000Mbps: On (yellow)
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* - LED[2]: high impedance (floating)
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*
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* Configure LEDs electrical polarity
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* - on-state: low
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* - off-state: high (not hi-z, to avoid residual glow)
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*/
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marvell,reg-init = <3 16 0xf000 0x0a61>,
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<3 17 0x003f 0x000a>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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};
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&cp0_pinctrl {
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pinctrl-0 = <&sim_select_pins>;
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pintrl-names = "default";
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rear_button_pins: cp0-rear-button-pins {
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marvell,pins = "mpp31";
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marvell,function = "gpio";
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};
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sim_select_pins: cp0-sim-select-pins {
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marvell,pins = "mpp27";
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marvell,function = "gpio";
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};
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};
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/*
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* SRDS #4 - USB 3.0 host on M.2 connector
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* USB-2.0 Host on Type-A connector
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*/
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&cp0_usb3_1 {
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phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
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phy-names = "comphy", "utmi";
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dr_mode = "host";
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status = "okay";
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};
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&expander0 {
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m2-full-card-power-off-hog {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "m2-full-card-power-off";
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};
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m2-reset-hog {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "m2-reset";
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};
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};
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375
arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
Normal file
375
arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
Normal file
@ -0,0 +1,375 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
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*
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* DTS for SolidRun CN9130 Clearfog Pro.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "cn9130.dtsi"
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#include "cn9130-sr-som.dtsi"
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#include "cn9130-cf.dtsi"
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/ {
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model = "SolidRun CN9130 Clearfog Pro";
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compatible = "solidrun,cn9130-clearfog-pro",
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"solidrun,cn9130-sr-som", "marvell,cn9130";
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button-0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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};
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/* SRDS #3 - SGMII 1GE to L2 switch */
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&cp0_eth1 {
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phys = <&cp0_comphy3 1>;
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phy-mode = "sgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&cp0_eth2_phy {
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/*
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* Configure LEDs default behaviour similar to switch ports:
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* - LED[0]: link/activity: On/blink (green)
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* - LED[1]: link is 100/1000Mbps: On (red)
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* - LED[2]: high impedance (floating)
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*
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* Switch port defaults:
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* - LED0: link/activity: On/blink (green)
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* - LED1: link is 1000Mbps: On (red)
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*
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* Identical configuration is impossible with hardware offload.
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*/
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marvell,reg-init = <3 16 0xf000 0x0a61>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WAN;
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label = "LED2";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_WAN;
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label = "LED1";
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default-state = "keep";
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};
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};
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};
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&cp0_mdio {
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ethernet-switch@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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pinctrl-0 = <&dsa_clk_pins &dsa_pins>;
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pinctrl-names = "default";
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reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&cp0_gpio1>;
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interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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reg = <0>;
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label = "lan5";
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phy = <&switch0phy0>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED12";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED11";
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default-state = "keep";
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};
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};
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan4";
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phy = <&switch0phy1>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED10";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED9";
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default-state = "keep";
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};
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};
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan3";
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phy = <&switch0phy2>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED8";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED7";
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default-state = "keep";
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};
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};
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan2";
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phy = <&switch0phy3>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED6";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED5";
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default-state = "keep";
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};
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};
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};
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ethernet-port@4 {
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reg = <4>;
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label = "lan1";
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phy = <&switch0phy4>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED4";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED3";
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default-state = "keep";
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};
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};
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};
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ethernet-port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&cp0_eth1>;
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phy-mode = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ethernet-port@6 {
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reg = <6>;
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label = "lan6";
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phy-mode = "rgmii";
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/*
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* Because of mdio address conflict the
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* external phy is not readable.
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* Force a fixed link instead.
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*/
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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switch0phy1: ethernet-phy@1 {
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reg = <0x1>;
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/*
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* Indirectly configure default behaviour
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* for port lan6 leds behind external phy.
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* Internal PHYs are not using page 3,
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* therefore writing to it is safe.
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*/
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marvell,reg-init = <3 16 0xf000 0x0a61>;
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};
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switch0phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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switch0phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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switch0phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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||||
};
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/*
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* There is an external phy on the switch mdio bus.
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* Because its mdio address collides with internal phys,
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* it is not readable.
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*
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* mdio-external {
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* compatible = "marvell,mv88e6xxx-mdio-external";
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* #address-cells = <1>;
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* #size-cells = <0>;
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*
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* ethernet-phy@1 {
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* reg = <0x1>;
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* };
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* };
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||||
*/
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||||
};
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||||
};
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||||
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||||
/* SRDS #4 - miniPCIe (CON2) */
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&cp0_pcie1 {
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num-lanes = <1>;
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||||
phys = <&cp0_comphy4 1>;
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||||
/* dw-pcie inverts internally */
|
||||
reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
dsa_clk_pins: cp0-dsa-clk-pins {
|
||||
marvell,pins = "mpp40";
|
||||
marvell,function = "synce1";
|
||||
};
|
||||
|
||||
dsa_pins: cp0-dsa-pins {
|
||||
marvell,pins = "mpp27", "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
rear_button_pins: cp0-rear-button-pins {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
/* add pin for chip-select 1 on mikrobus */
|
||||
pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
|
||||
};
|
||||
|
||||
/* USB-2.0 Host on Type-A connector */
|
||||
&cp0_usb3_1 {
|
||||
phys = <&cp0_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&expander0 {
|
||||
/* CON2 */
|
||||
pcie1-0-clkreq-hog {
|
||||
gpio-hog;
|
||||
gpios = <4 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "pcie1.0-clkreq";
|
||||
};
|
||||
|
||||
/* CON2 */
|
||||
pcie1-0-w-disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <7 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie1.0-w-disable";
|
||||
};
|
||||
};
|
||||
197
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
Normal file
197
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
Normal file
@ -0,0 +1,197 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* DTS for common base of SolidRun CN9130 Clearfog Base and Pro.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
/* label nics same order as armada 388 clearfog */
|
||||
ethernet0 = &cp0_eth2;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth0;
|
||||
i2c1 = &cp0_i2c1;
|
||||
mmc1 = &cp0_sdhci0;
|
||||
};
|
||||
|
||||
reg_usb3_vbus0: regulator-usb3-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sfp: sfp {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp0_i2c1>;
|
||||
los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #2 - SFP+ 10GE */
|
||||
&cp0_eth0 {
|
||||
managed = "in-band-status";
|
||||
phys = <&cp0_comphy2 0>;
|
||||
phy-mode = "10gbase-r";
|
||||
sfp = <&sfp>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
expander0: gpio-expander@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
pinctrl-0 = <&expander0_pins>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
/* CON3 */
|
||||
pcie2-0-clkreq-hog {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "pcie2.0-clkreq";
|
||||
};
|
||||
|
||||
/* CON3 */
|
||||
pcie2-0-w-disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie2.0-w-disable";
|
||||
};
|
||||
|
||||
usb3-ilimit-hog {
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "usb3-current-limit";
|
||||
};
|
||||
|
||||
m2-devslp-hog {
|
||||
gpio-hog;
|
||||
gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "m.2 devslp";
|
||||
};
|
||||
};
|
||||
|
||||
/* The MCP3021 supports standard and fast modes */
|
||||
adc@4c {
|
||||
compatible = "microchip,mcp3021";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
carrier_eeprom: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
/*
|
||||
* Routed to SFP, M.2, mikrobus, and miniPCIe
|
||||
* SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
|
||||
* address pins tied low, which takes addresses 0x50 and 0x51.
|
||||
* Mikrobus doesn't specify beyond an I2C bus being present.
|
||||
* PCIe uses ARP to assign addresses, or 0x63-0x64.
|
||||
*/
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - miniPCIe (CON3) */
|
||||
&cp0_pcie2 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp0_comphy5 2>;
|
||||
/* dw-pcie inverts internally */
|
||||
reset-gpios = <&expander0 1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
cp0_i2c1_pins: cp0-i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
cp0_mmc0_pins: cp0-mmc0-pins {
|
||||
marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
|
||||
mikro_spi_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
mikro_uart_pins: cp0-uart-pins {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "uart1";
|
||||
};
|
||||
|
||||
expander0_pins: cp0-expander0-pins {
|
||||
marvell,pins = "mpp4";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0 - SATA on M.2 connector */
|
||||
&cp0_sata0 {
|
||||
phys = <&cp0_comphy0 1>;
|
||||
status = "okay";
|
||||
|
||||
/* only port 1 is available */
|
||||
/delete-node/ sata-port@0;
|
||||
};
|
||||
|
||||
/* microSD */
|
||||
&cp0_sdhci0 {
|
||||
pinctrl-0 = <&cp0_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
/* CS1 for mikrobus */
|
||||
pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>;
|
||||
};
|
||||
|
||||
/*
|
||||
* SRDS #1 - USB-3.0 Host on Type-A connector
|
||||
* USB-2.0 Host on mPCI-e connector (CON3)
|
||||
*/
|
||||
&cp0_usb3_0 {
|
||||
phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
|
||||
phy-names = "comphy", "utmi";
|
||||
vbus-supply = <®_usb3_vbus0>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* mikrobus uart */
|
||||
&cp0_uart0 {
|
||||
pinctrl-0 = <&mikro_uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
160
arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
Normal file
160
arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
Normal file
@ -0,0 +1,160 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 SoM";
|
||||
compatible = "solidrun,cn9130-sr-som", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth2;
|
||||
i2c0 = &cp0_i2c0;
|
||||
mmc0 = &ap_sdhci0;
|
||||
rtc0 = &cp0_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
v_1_8: regulator-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
/* requires assembly of R9307 */
|
||||
vhv: regulator-vhv-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vhv-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
pinctrl-0 = <&cp0_reg_vhv_pins>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&cp0_gpio2 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ap_pinctrl {
|
||||
ap_mmc0_pins: ap-mmc0-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
|
||||
marvell,function = "sdio";
|
||||
/*
|
||||
* mpp12 is emmc reset, function should be sdio (hw_rst),
|
||||
* but pinctrl-mvebu does not support this.
|
||||
*
|
||||
* From pinctrl-mvebu.h:
|
||||
* "The name will be used to switch to this setting in DT description, e.g.
|
||||
* marvell,function = "uart2". subname is only for debugging purposes."
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
&ap_sdhci0 {
|
||||
bus-width = <8>;
|
||||
pinctrl-0 = <&ap_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
vqmmc-supply = <&v_1_8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for assembly with phy */
|
||||
&cp0_eth2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_eth2_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy = <&cp0_eth2_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
som_eeprom: eeprom@53 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x53>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
pinctrl-0 = <&cp0_mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
/* assembly option */
|
||||
cp0_eth2_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi1_pins>;
|
||||
/* max speed limited by a mux */
|
||||
spi-max-frequency = <1800000000>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/* read command supports max. 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_eth2_pins: cp0-ge2-rgmii-pins {
|
||||
marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47",
|
||||
"mpp48", "mpp49", "mpp50", "mpp51",
|
||||
"mpp52", "mpp53", "mpp54", "mpp55";
|
||||
/* docs call it "ge2", but cp110-pinctrl "ge1" */
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
cp0_mdio_pins: cp0-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
cp0_spi1_pins: cp0-spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp0_reg_vhv_pins: cp0-reg-vhv-pins {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AP default console */
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user