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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: qcom: x1e80100: Add display nodes
Add the required nodes to support display on X1E80100. Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-8-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa
Bjorn Andersson
parent
5eb83fc102
commit
1940c25eaa
@ -4,6 +4,7 @@
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*/
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
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#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
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#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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@ -3352,6 +3353,524 @@ usb_1_ss1_role_switch: endpoint {
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};
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};
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mdss: display-subsystem@ae00000 {
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compatible = "qcom,x1e80100-mdss";
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reg = <0 0x0ae00000 0 0x1000>;
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reg-names = "mdss";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "mdp0-mem",
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"mdp1-mem",
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"cpu-cfg";
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power-domains = <&dispcc MDSS_GDSC>;
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iommus = <&apps_smmu 0x1c00 0x2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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mdss_mdp: display-controller@ae01000 {
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compatible = "qcom,x1e80100-dpu";
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reg = <0 0x0ae01000 0 0x8f000>,
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<0 0x0aeb0000 0 0x2008>;
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reg-names = "mdp",
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"vbif";
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interrupts-extended = <&mdss 0>;
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_intf0_out: endpoint {
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remote-endpoint = <&mdss_dp0_in>;
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};
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};
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port@4 {
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reg = <4>;
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mdss_intf4_out: endpoint {
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remote-endpoint = <&mdss_dp1_in>;
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};
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};
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port@5 {
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reg = <5>;
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mdss_intf5_out: endpoint {
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remote-endpoint = <&mdss_dp3_in>;
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};
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};
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port@6 {
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reg = <6>;
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mdss_intf6_out: endpoint {
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remote-endpoint = <&mdss_dp2_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-514000000 {
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opp-hz = /bits/ 64 <514000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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opp-575000000 {
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opp-hz = /bits/ 64 <575000000>;
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required-opps = <&rpmhpd_opp_nom_l1>;
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};
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};
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};
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mdss_dp0: displayport-controller@ae90000 {
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compatible = "qcom,x1e80100-dp";
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reg = <0 0xae90000 0 0x200>,
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<0 0xae90200 0 0x200>,
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<0 0xae90400 0 0x600>,
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<0 0xae91000 0 0x400>,
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<0 0xae91400 0 0x400>;
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interrupts-extended = <&mdss 12>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
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assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&mdss_dp0_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp0_in: endpoint {
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remote-endpoint = <&mdss_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dp0_out: endpoint {
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};
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};
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};
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mdss_dp0_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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mdss_dp1: displayport-controller@ae98000 {
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compatible = "qcom,x1e80100-dp";
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reg = <0 0xae98000 0 0x200>,
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<0 0xae98200 0 0x200>,
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<0 0xae98400 0 0x600>,
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<0 0xae99000 0 0x400>,
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<0 0xae99400 0 0x400>;
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interrupts-extended = <&mdss 13>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
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assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&mdss_dp1_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp1_in: endpoint {
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remote-endpoint = <&mdss_intf4_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dp1_out: endpoint {
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};
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};
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};
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mdss_dp1_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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mdss_dp2: displayport-controller@ae9a000 {
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compatible = "qcom,x1e80100-dp";
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reg = <0 0xae9a000 0 0x200>,
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<0 0xae9a200 0 0x200>,
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<0 0xae9a400 0 0x600>,
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<0 0xae9b000 0 0x400>,
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<0 0xae9b400 0 0x400>;
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interrupts-extended = <&mdss 14>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dp2_phy 0>,
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<&mdss_dp2_phy 1>;
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operating-points-v2 = <&mdss_dp2_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dp2_phy>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp2_in: endpoint {
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remote-endpoint = <&mdss_intf6_out>;
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};
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};
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port@1 {
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reg = <1>;
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};
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};
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mdss_dp2_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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mdss_dp3: displayport-controller@aea0000 {
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compatible = "qcom,x1e80100-dp";
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reg = <0 0xaea0000 0 0x200>,
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<0 0xaea0200 0 0x200>,
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<0 0xaea0400 0 0x600>,
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<0 0xaea1000 0 0x400>,
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<0 0xaea1400 0 0x400>;
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interrupts-extended = <&mdss 15>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dp3_phy 0>,
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<&mdss_dp3_phy 1>;
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operating-points-v2 = <&mdss_dp3_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dp3_phy>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp3_in: endpoint {
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remote-endpoint = <&mdss_intf5_out>;
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link-frequencies = /bits/ 64 <8100000000>;
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};
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};
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port@1 {
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reg = <1>;
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};
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};
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mdss_dp3_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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};
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mdss_dp2_phy: phy@aec2a00 {
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compatible = "qcom,x1e80100-dp-phy";
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reg = <0 0x0aec2a00 0 0x19c>,
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<0 0x0aec2200 0 0xec>,
|
||||
<0 0x0aec2600 0 0xec>,
|
||||
<0 0x0aec2000 0 0x1c8>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb";
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MX>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdss_dp3_phy: phy@aec5a00 {
|
||||
compatible = "qcom,x1e80100-dp-phy";
|
||||
reg = <0 0x0aec5a00 0 0x19c>,
|
||||
<0 0x0aec5200 0 0xec>,
|
||||
<0 0x0aec5600 0 0xec>,
|
||||
<0 0x0aec5000 0 0x1c8>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb";
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MX>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dispcc: clock-controller@af00000 {
|
||||
compatible = "qcom,x1e80100-dispcc";
|
||||
reg = <0 0x0af00000 0 0x20000>;
|
||||
clocks = <&bi_tcxo_div2>,
|
||||
<&bi_tcxo_ao_div2>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<0>, /* dsi0 */
|
||||
<0>,
|
||||
<0>, /* dsi1 */
|
||||
<0>,
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&mdss_dp2_phy 0>, /* dp2 */
|
||||
<&mdss_dp2_phy 1>,
|
||||
<&mdss_dp3_phy 0>, /* dp3 */
|
||||
<&mdss_dp3_phy 1>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
|
||||
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user