mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: qcom: sm8450: add Soundwire and LPASS
Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and LPASS pin controller. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202152054.357316-3-krzysztof.kozlowski@linaro.org
This commit is contained in:
Srinivas Kandagatla
Bjorn Andersson
parent
38463210a9
commit
14341e76db
@ -15,6 +15,7 @@
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/soc/qcom,gpr.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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@ -2098,6 +2099,209 @@ compute-cb@3 {
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};
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};
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wsa2macro: codec@31e0000 {
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compatible = "qcom,sm8450-lpass-wsa-macro";
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reg = <0 0x031e0000 0 0x1000>;
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clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&vamacro>;
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clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
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assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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assigned-clock-rates = <19200000>, <19200000>;
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#clock-cells = <0>;
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clock-output-names = "wsa2-mclk";
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pinctrl-names = "default";
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pinctrl-0 = <&wsa2_swr_active>;
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#sound-dai-cells = <1>;
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};
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/* WSA2 */
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swr4: soundwire-controller@31f0000 {
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compatible = "qcom,soundwire-v1.7.0";
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reg = <0 0x031f0000 0 0x2000>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wsa2macro>;
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clock-names = "iface";
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qcom,din-ports = <2>;
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qcom,dout-ports = <6>;
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qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
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qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
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qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
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qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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#address-cells = <2>;
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#size-cells = <0>;
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#sound-dai-cells = <1>;
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};
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rxmacro: codec@3200000 {
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compatible = "qcom,sm8450-lpass-rx-macro";
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reg = <0 0x3200000 0 0x1000>;
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clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&vamacro>;
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clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
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assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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assigned-clock-rates = <19200000>, <19200000>;
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#clock-cells = <0>;
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clock-output-names = "mclk";
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pinctrl-names = "default";
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pinctrl-0 = <&rx_swr_active>;
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#sound-dai-cells = <1>;
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};
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swr1: soundwire-controller@3210000 {
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compatible = "qcom,soundwire-v1.7.0";
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reg = <0 0x3210000 0 0x2000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rxmacro>;
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clock-names = "iface";
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label = "RX";
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qcom,din-ports = <0>;
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qcom,dout-ports = <5>;
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qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
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qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
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qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
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qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
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qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
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#address-cells = <2>;
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#size-cells = <0>;
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#sound-dai-cells = <1>;
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};
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txmacro: codec@3220000 {
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compatible = "qcom,sm8450-lpass-tx-macro";
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reg = <0 0x3220000 0 0x1000>;
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clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&vamacro>;
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clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
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assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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assigned-clock-rates = <19200000>, <19200000>;
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#clock-cells = <0>;
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clock-output-names = "mclk";
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pinctrl-names = "default";
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pinctrl-0 = <&tx_swr_active>;
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#sound-dai-cells = <1>;
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};
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wsamacro: codec@3240000 {
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compatible = "qcom,sm8450-lpass-wsa-macro";
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reg = <0 0x03240000 0 0x1000>;
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clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&vamacro>;
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clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
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assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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assigned-clock-rates = <19200000>, <19200000>;
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#clock-cells = <0>;
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clock-output-names = "mclk";
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pinctrl-names = "default";
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pinctrl-0 = <&wsa_swr_active>;
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#sound-dai-cells = <1>;
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};
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/* WSA */
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swr0: soundwire-controller@3250000 {
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compatible = "qcom,soundwire-v1.7.0";
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reg = <0 0x03250000 0 0x2000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wsamacro>;
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clock-names = "iface";
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qcom,din-ports = <2>;
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qcom,dout-ports = <6>;
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qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
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qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
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qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
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qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
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#address-cells = <2>;
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#size-cells = <0>;
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#sound-dai-cells = <1>;
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};
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swr2: soundwire-controller@33b0000 {
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compatible = "qcom,soundwire-v1.7.0";
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reg = <0 0x33b0000 0 0x2000>;
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interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "core", "wake";
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clocks = <&vamacro>;
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clock-names = "iface";
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label = "TX";
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qcom,din-ports = <4>;
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qcom,dout-ports = <0>;
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qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
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qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
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qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
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qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
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#address-cells = <2>;
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#size-cells = <0>;
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#sound-dai-cells = <1>;
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};
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vamacro: codec@33f0000 {
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compatible = "qcom,sm8450-lpass-va-macro";
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reg = <0 0x033f0000 0 0x1000>;
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clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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clock-names = "mclk", "macro", "dcodec", "npl";
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assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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assigned-clock-rates = <19200000>;
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#clock-cells = <0>;
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clock-output-names = "fsgen";
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#sound-dai-cells = <1>;
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};
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remoteproc_adsp: remoteproc@30000000 {
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compatible = "qcom,sm8450-adsp-pas";
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reg = <0 0x30000000 0 0x100>;
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@ -3031,6 +3235,123 @@ qup_uart20_default: qup-uart20-default-state {
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};
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lpass_tlmm: pinctrl@3440000{
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compatible = "qcom,sm8450-lpass-lpi-pinctrl";
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reg = <0 0x3440000 0x0 0x20000>,
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<0 0x34d0000 0x0 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&lpass_tlmm 0 0 23>;
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clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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clock-names = "core", "audio";
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tx_swr_active: tx-swr-active-state {
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clk-pins {
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pins = "gpio0";
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function = "swr_tx_clk";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-disable;
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};
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data-pins {
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pins = "gpio1", "gpio2", "gpio14";
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function = "swr_tx_data";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-bus-hold;
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};
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};
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rx_swr_active: rx-swr-active-state {
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clk-pins {
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pins = "gpio3";
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function = "swr_rx_clk";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-disable;
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};
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data-pins {
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pins = "gpio4", "gpio5";
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function = "swr_rx_data";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-bus-hold;
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};
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};
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dmic01_default: dmic01-default-state {
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clk-pins {
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pins = "gpio6";
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function = "dmic1_clk";
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drive-strength = <8>;
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output-high;
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};
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data-pins {
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pins = "gpio7";
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function = "dmic1_data";
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drive-strength = <8>;
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input-enable;
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};
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};
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dmic02_default: dmic02-default-state {
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clk-pins {
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pins = "gpio8";
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function = "dmic2_clk";
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drive-strength = <8>;
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output-high;
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};
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data-pins {
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pins = "gpio9";
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function = "dmic2_data";
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drive-strength = <8>;
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input-enable;
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};
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};
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wsa_swr_active: wsa-swr-active-state {
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clk-pins {
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pins = "gpio10";
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function = "wsa_swr_clk";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-disable;
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};
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data-pins {
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pins = "gpio11";
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function = "wsa_swr_data";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-bus-hold;
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};
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};
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wsa2_swr_active: wsa2-swr-active-state {
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clk-pins {
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pins = "gpio15";
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function = "wsa2_swr_clk";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-disable;
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};
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data-pins {
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pins = "gpio16";
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function = "wsa2_swr_data";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-bus-hold;
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};
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};
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};
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apps_smmu: iommu@15000000 {
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compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
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reg = <0 0x15000000 0 0x100000>;
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@ -3510,6 +3831,9 @@ lpass_ag_noc: interconnect@3c40000 {
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};
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};
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sound: sound {
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};
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thermal-zones {
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aoss0-thermal {
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polling-delay-passive = <0>;
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