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arm64: dts: qcom: sm8450: Add remoteproc enablers and instances
The Qualcomm SM8450 carries the familiar set of audio, compute, sensor and modem remoteprocs. Add these and their dependencies. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220128025513.97188-13-bjorn.andersson@linaro.org
This commit is contained in:
Bjorn Andersson
parent
73419e4d2f
commit
1172729576
@ -7,6 +7,7 @@
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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@ -460,6 +461,15 @@ cvp_mem: memory@9ee00000 {
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no-map;
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};
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rmtfs_mem: memory@9fd00000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0x0 0x9fd00000 0x0 0x280000>;
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no-map;
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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global_sync_mem: memory@a6f00000 {
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reg = <0x0 0xa6f00000 0x0 0x100000>;
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no-map;
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@ -540,6 +550,113 @@ trusted_apps_ext_mem: memory@ed900000 {
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};
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};
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smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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smp2p_adsp_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_adsp_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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smp2p_cdsp_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_cdsp_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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smp2p_modem_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_modem_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ipa_smp2p_out: ipa-ap-to-modem {
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qcom,entry-name = "ipa";
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#qcom,smem-state-cells = <1>;
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};
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ipa_smp2p_in: ipa-modem-to-ap {
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qcom,entry-name = "ipa";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-slpi {
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compatible = "qcom,smp2p";
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qcom,smem = <481>, <430>;
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interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <3>;
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smp2p_slpi_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_slpi_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -672,6 +789,167 @@ usb_1_ssphy: phy@88e9200 {
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};
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};
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remoteproc_slpi: remoteproc@2400000 {
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compatible = "qcom,sm8450-slpi-pas";
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reg = <0 0x02400000 0 0x4000>;
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interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8450_LCX>,
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<&rpmhpd SM8450_LMX>;
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power-domain-names = "lcx", "lmx";
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memory-region = <&slpi_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_slpi_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "slpi";
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qcom,remote-pid = <3>;
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};
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};
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remoteproc_adsp: remoteproc@30000000 {
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compatible = "qcom,sm8450-adsp-pas";
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reg = <0 0x030000000 0 0x100>;
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interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8450_LCX>,
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<&rpmhpd SM8450_LMX>;
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power-domain-names = "lcx", "lmx";
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memory-region = <&adsp_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_adsp_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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remoteproc_adsp_glink: glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "lpass";
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qcom,remote-pid = <2>;
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};
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};
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remoteproc_cdsp: remoteproc@32300000 {
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compatible = "qcom,sm8450-cdsp-pas";
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reg = <0 0x032300000 0 0x1400000>;
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interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8450_CX>,
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<&rpmhpd SM8450_MXC>;
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power-domain-names = "cx", "mxc";
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memory-region = <&cdsp_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_cdsp_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "cdsp";
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qcom,remote-pid = <5>;
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};
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};
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remoteproc_mpss: remoteproc@4080000 {
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compatible = "qcom,sm8450-mpss-pas";
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reg = <0x0 0x04080000 0x0 0x4040>;
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interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready", "handover",
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"stop-ack", "shutdown-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd 0>,
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<&rpmhpd 12>;
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power-domain-names = "cx", "mss";
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memory-region = <&mpss_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_modem_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
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label = "modem";
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qcom,remote-pid = <1>;
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8450-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
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@ -682,6 +960,25 @@ pdc: interrupt-controller@b220000 {
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interrupt-controller;
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};
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aoss_qmp: power-controller@c300000 {
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compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
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reg = <0 0x0c300000 0 0x400>;
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interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
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#clock-cells = <0>;
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};
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ipcc: mailbox@ed18000 {
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compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
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reg = <0 0x0ed18000 0 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sm8450-tlmm";
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reg = <0 0x0f100000 0 0x300000>;
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