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arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk

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The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-2-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong 2024-05-02 10:00:37 +02:00 committed by Bjorn Andersson
parent e768628406
commit 0cc97d9e3f
4 changed files with 4 additions and 36 deletions
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4
arch/arm64/boot/dts/qcom/sm8550-hdk.dts
View File

@ -978,10 +978,6 @@ &pcie1_phy {
status = "okay"; status = "okay";
}; };
&pcie_1_phy_aux_clk {
clock-frequency = <1000>;
};
&pm8550_gpios { &pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state { sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12"; pins = "gpio12";

4
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
View File

@ -738,10 +738,6 @@ &mdss_dp0_out {
data-lanes = <0 1>; data-lanes = <0 1>;
}; };
&pcie_1_phy_aux_clk {
clock-frequency = <1000>;
};
&pcie0 { &pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

19
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
View File

@ -720,17 +720,6 @@ &ipa {
status = "okay"; status = "okay";
}; };
&gcc {
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
};
&gpi_dma1 { &gpi_dma1 {
status = "okay"; status = "okay";
}; };
@ -809,10 +798,6 @@ &mdss_dp0_out {
data-lanes = <0 1>; data-lanes = <0 1>;
}; };
&pcie_1_phy_aux_clk {
status = "disabled";
};
&pcie0 { &pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@ -906,10 +891,6 @@ &pon_resin {
status = "okay"; status = "okay";
}; };
&pcie_1_phy_aux_clk {
clock-frequency = <1000>;
};
&qupv3_id_0 { &qupv3_id_0 {
status = "okay"; status = "okay";
}; };

13
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-mult = <1>; clock-mult = <1>;
clock-div = <2>; clock-div = <2>;
}; };
pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
}; };
cpus { cpus {
@ -776,8 +771,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>; #power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>, clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>, <&pcie0_phy>,
<&pcie1_phy>, <&pcie1_phy QMP_PCIE_PIPE_CLK>,
<&pcie_1_phy_aux_clk>, <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 0>,
<&ufs_mem_phy 1>, <&ufs_mem_phy 1>,
<&ufs_mem_phy 2>, <&ufs_mem_phy 2>,
@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>; power-domains = <&gcc PCIE_1_PHY_GDSC>;
#clock-cells = <0>; #clock-cells = <1>;
clock-output-names = "pcie1_pipe_clk"; clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
#phy-cells = <0>; #phy-cells = <0>;