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Issue : Configuring TemporaryRamSize using FSP-T arch UPD (added as part of Spec 2.5) is not working as expected. Root cause : Code is reading the ImageAttribute from the wrong address which confirms the TemporaryRamSize Configurability, hence the TemporaryRamSize UPD is ignored. This is because the code expects the FspInfoheader Offset to be in ESI/RSI (from which ImageAttribute read) is not guaranteed as per the current implementation. Fix : Modified code to make sure that ESI/RSI contains the FspInfoheader offset by time the code reads the ImageAttribute. Tests : Verified the fix on Both 32 Bit and 64 Bit FSP Binaries by configuring the TemporaryRamSize using the FSPT Arch UPD. Signed-off-by: Aravind P R <aravind.p.r@intel.com> |
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| .. | ||
| Fsp22ApiEntryS.nasm | ||
| Fsp24ApiEntryM.nasm | ||
| Fsp24ApiEntryS.nasm | ||
| FspApiEntryCommon.nasm | ||
| FspApiEntryI.nasm | ||
| FspApiEntryM.nasm | ||
| FspApiEntryS.nasm | ||
| FspApiEntryT.nasm | ||
| FspHelper.nasm | ||
| MicrocodeLoadNasm.inc | ||
| ReadEsp.nasm | ||
| SaveRestoreSseNasm.inc | ||
| Stack.nasm | ||